My textbook tells me that "the 9-bit address [of instruction format d-format] means a load register instruction can load any doubleword within a region of +/- 2^8 or 256 bytes of the address in the base register Rn." But why is it +/- 2^8 bytes and not +/- 2^9 bytes, since there are 9 bits in the address? And why is it +/- and not just +, since I doubt there can be a negative address? Or is the address signed but the Rn and Rt bits aren't?
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In the document,
PCI Bus Binding to: IEEE Std 1275-1994 Standard for Boot (Initialization Configuration) Firmware
it says, for the Memory Space,
The encoding of the base address registers for Memory Space allows a
resource to require address allocation within the first 1 MB. This
requirement is reflected in the "reg" property entry for that base
register by having the 't' bit set.
Also, for the IO space,
PCI also allows devices to have I/O base address registers that
implement only the low-order 16 bits. I.e., the upper 16 bits are
assumed to be 0. When probing, after writing all 1s, the data read
back will have the high-order 16 bits equal to 0, while the low-order
16 bits will reflect the address space requirement.
Address space for such a base register must be allocated within the
first 64 KB of I/O Space. This requirement is reflected in the "reg"
property for that base register by having the 't'-bit set.
But what is this 't' bit? The document later says about PCI address representation that uses 3 bit 'npt' values. I already knew for specifying "ranges" property, the child address (PCI address) uses 3 cells and the first 32bit contains 'n','p','t' bits at the MSB bits to express non-relocatable, prefetchable and the type(meaning varies according to address space type). But "reg" property in dts normally represents the register regions representing the start and size and doesn't use this npt values but just physical address. So I'm confused. https://elinux.org/Device_Tree_Usage#PCI_Address_Translation)
Considering multilevel paging, If we have a physical address of 32 bits, say 24 bits are allocated for frame number. Whenever a Virtual address is generated, it goes to Page Table and the PTE is 24 bits(ignore control bits) gives frame no. But these 24 bits cannot actually find an address .
So my question is, Are these 24 bits right padded with zeros to reach the base address of that frame ?
It is said that 8086 Microprocessor has 1MB Memory and 20-bit address, 16- bit data bus . My doubt is that if it is 1MB memory that means (2^20 * 2^3) (1 byte = 8 bits) bits or 2^ 23 bits is the whole memory size. Then as 8086 is a 16- bit register then 2^20 ( from address lines) * 2^4( 16- bit size) is the memory i.e 2^ 24 bits which is not what I calculated above.
So there is a false in my assessment , what is that ?.
Each of the 2^20 addresses refers to an 8-bit Byte.
Some of the 8086's machine instructions operate on Bytes (8-bits) (using registers AH, AL, BH, BL, ...) and other machine instructions operate on Words (16-bits) (using registers AX, BX, ...).
When using a Word instruction, two adjacent bytes in memory (addresses (a) and (a+1)) are treated as a Word datum. I do not recall if the 8086 enforces even address alignment for Word-datum memory references. But, 2^20 Bytes contains only 2^19 Words (aligned to even addresses).
Bits are conserved:
(2^20 * 2^3) = (2^19 * 2^4) = 2^23
"The address consists of 16 bits, and the page size is 8KB. The page table thus consists of eight entries that are kept in fast registers."
How do we get the total entries in the page table as 8?
According to the calculation it should be 1.
Total Entries in the Page Table= ((2^16)/(2^3*2^10*2^3))=1.
(The first 2^3 is for 8 in 8KB, the second one is for bytes to bits conversion and 2^10 is for "Kilo" in 8KB.)
Thanks
Memory is byte-addressable hence, you do not need to divide by 2^3 for bytes to bit conversion.
Explaining it further, 16-bits for address means that the processor will generate memory addresses of length 16 bits which will be used to address the byte or half-word or word present starting (or ending - depends on the endianess of the machine) at that 16-bit value.
Now, the page size is the total size of a page in bits which in this case is 2^16 bits. But as memory is byte addressable, hence number of processor addresses in one page will be 2^16/2^3 i.e 2^13 addresses.
Hence number of page table entries are 2^16/2^13 = 8.
I learnt that the physical address is calculated by shifting the segment address (16-bit) left 4 times and adding it with the 16-bit offset address. The memory in the 8086 architecture is 1M.
My question is if the segment register and the offset value both are FFFFH and FFFFH then the result would be more than FFFFH i.e., more than 1M.
FFFF0
+ FFFF
----------
10FFEF
haw is it actually calculated...??
It does modular arithmetic, dropping any carries. So for a segment of FFFF and offset of FFFF, you compute FFFF0 + FFFF = 10FFEF but it "drops" the initial 1, leaving a real answer of 0FFEF.
The 8086 address bus is only 20 bits wide, which gives a max high address of 0xFFFFF = 1,048,575. It's calculated just the way you did it, but only the low-order 20 bits are used in the memory fetch.