It is said that 8086 Microprocessor has 1MB Memory and 20-bit address, 16- bit data bus . My doubt is that if it is 1MB memory that means (2^20 * 2^3) (1 byte = 8 bits) bits or 2^ 23 bits is the whole memory size. Then as 8086 is a 16- bit register then 2^20 ( from address lines) * 2^4( 16- bit size) is the memory i.e 2^ 24 bits which is not what I calculated above.
So there is a false in my assessment , what is that ?.
Each of the 2^20 addresses refers to an 8-bit Byte.
Some of the 8086's machine instructions operate on Bytes (8-bits) (using registers AH, AL, BH, BL, ...) and other machine instructions operate on Words (16-bits) (using registers AX, BX, ...).
When using a Word instruction, two adjacent bytes in memory (addresses (a) and (a+1)) are treated as a Word datum. I do not recall if the 8086 enforces even address alignment for Word-datum memory references. But, 2^20 Bytes contains only 2^19 Words (aligned to even addresses).
Bits are conserved:
(2^20 * 2^3) = (2^19 * 2^4) = 2^23
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I'm learning the concept of directed mapped cache, but I don't get it how to get cache memory size and main memory size by using block size. (The unit is bytes.) the given values are 2^3 words = 2^5 bytes of block size, 4 bits of tags(0000~1111) and 3 bits of the index(000~111).
the questions >>
what's the size of cache memory and main memory in each?
and which address do we insert in each data part?
I already tried to separate the part tag and the cache index. I insert the tag on 3 upper order bits and insert the cache index(29 bits) on the remaining space. I got the main memory size, 4GB, and the cache size, 2^29 bytes. but I think something is wrong. I feel that I don't understand the concept of this.
Your answer is incorrect, because you are assuming address is 32 bits and it is byte addressable, hence the 4GB memory size. This is not true and we must first compute these values.
8 words = 32 bytes = block size
So offset=3 bits (to address 8 words in a block)
and word size=4 bytes/word (32 bytes/8 words)
We have now the width of an address: 4 bits (tag) + 3 bits (index) + 3 bits (offset)= 10 bits.
With 10 bits address, main memory is 2^10 words=2^12 bytes=4kB
Cache has 8 blocks (3 bits index), each block has 32 bytes and cache size=8*32 bytes=256B.
In a MIPS processor, I/O address space 0xffff0000 to 0xffffffff is reserved for memory-mapped I/O. Assuming that an I/O device needs 3, 1, and 4 32-bit words for control, status and data registers respecitvely. How many I/O devices can be supported?
The correct answer is 2048, but I got 8192.
My thought process:
Subtract the two spaces to retrieve the amount of memory needed
ffffffff - ffff0000 = 0000ffff = 65535 bits = 2^16 - 1
Then divide by 32-bits and multiply by 8, but that is obviously wrong.
Can someone guide me through the steps to get the correct answer? Thank you
Each devices uses: (3+1+4) * 32 bits = 8 * 4 bytes = 32 bytes
The available memory area is in bytes, not bits : 2^16 = 65536 bytes
Thus, you have: 65536 bytes / 32 bytes = 2048.
So 2048 devices are supported.
How would I convert a 16K x 32 SRAM into a 64K x 8 SRAM? The 16K x 32 RAM module is a single unit that cannot be altered internally and is capable of address decoding, has tristate outputs, and read/write/and chip enable. Also only the memory read of the circuit has to be implemented.
The 16K x 32 SRAM accepts a 14-bit address and produces a 32-bit value. However, the 64K x 8 SRAM accepts a 16-bit address and produces an 8-bit value. You can design a circuit whose interface exactly matches the interface of a 64K x 8 SRAM module. However, internally, it sends the most significant 14 bits of the supplied 16-bit address to the 16K x 32 SRAM together with the control signals. Then it uses the least significant 2 bits of the 16-bit address to select an 8-bit value from the 32-bit value produced by the 16K x 32 SRAM. Finally, the resulting 8-bit value is sent to the output pins of the circuit.
Essentially, how does 4Gb turn into 4GB? If the memory is addressing Bytes, should not the possibilities be 2(32/8)?
It depends on how you address the data.
If you use 32 bits to address each bit, you can address 232 bits or 4Gb = 512MB. If you address bytes like most current architectures it will give you 4GB.
But if you address much larger blocks you will need less bits to address 4GB. For example if you address each 512-byte block (29 bytes) you can address 4GB with 23 bits. FAT16 uses 16 bits to address (maximum) 64KB clusters and therefore can address a maximum 4GB volume. The same is used in Java Compressed Oops where you can address 32GB of memory with 32-bit reference.
Some older architectures even use word-addressable memory instead of byte like most do nowadays. Modern architectures that have a minimum addressable unit bigger than an octet are mainly found in DSPs. There also a few architectures with bit-addressable memory like Intel 8051
Most modern computers are byte-addressable, with each address identifying a single eight bit byte of storage; data too large to be stored in a single byte may reside in multiple bytes occupying a sequence of consecutive addresses.
There exist word-addressable computers, where minimal addressable storage unit is exactly the processor's word. For example, the Data General Nova minicomputer, and the Texas Instruments TMS9900 and National Semiconductor IMP-16 microcomputers used 16 bit words, and there were many 36-bit mainframe computers (e.g., PDP-10) which used 18-bit word addressing, not byte addressing, giving an address space of 218 36-bit words, approximately 1 megabyte of storage.
The efficiency of addressing of memory depends on the bit size of the bus used for addresses – the more bits used, the more addresses are available to the computer. For example, an 8-bit-byte-addressable machine with a 20-bit address bus (e.g. Intel 8086) can address 220 (1,048,576) memory locations, or one MiB of memory, while a 32-bit bus (e.g. Intel 80386) addresses 232 (4,294,967,296) locations, or a 4 GiB address space.
The electrical interface on the chip consists (extremely simplified) of a wires for the address (e.g. 32 address lines) and wires for the data (e.g. 8 wires for read data coming from the RAM, 8 wires for write data going to the RAM). In this case you have 232 words of 8 bits, so you can address 232*8 bits of data.
If you had a RAM with a word width of 16-bit instead (much more likely than 8-bit) you would be able to address twice as much RAM with the same number of address bits. On a modern system, you cannot really "read one byte" but instead the CPU fetches a whole cache line from the RAM and then gives you back just the byte that you asked for.
You can address 2 fields in memory with 1 bits.
You can address 4 fields in memory with 2 bits.
00, 01, 10, 11
So we can address memory by 2^n. For 32bit memory that each address holds 1byte can address 4GB data.
2^32 = 4.294.967.296 address can hold 4GByte data.
I learnt that the physical address is calculated by shifting the segment address (16-bit) left 4 times and adding it with the 16-bit offset address. The memory in the 8086 architecture is 1M.
My question is if the segment register and the offset value both are FFFFH and FFFFH then the result would be more than FFFFH i.e., more than 1M.
FFFF0
+ FFFF
----------
10FFEF
haw is it actually calculated...??
It does modular arithmetic, dropping any carries. So for a segment of FFFF and offset of FFFF, you compute FFFF0 + FFFF = 10FFEF but it "drops" the initial 1, leaving a real answer of 0FFEF.
The 8086 address bus is only 20 bits wide, which gives a max high address of 0xFFFFF = 1,048,575. It's calculated just the way you did it, but only the low-order 20 bits are used in the memory fetch.