Considering multilevel paging, If we have a physical address of 32 bits, say 24 bits are allocated for frame number. Whenever a Virtual address is generated, it goes to Page Table and the PTE is 24 bits(ignore control bits) gives frame no. But these 24 bits cannot actually find an address .
So my question is, Are these 24 bits right padded with zeros to reach the base address of that frame ?
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Consider the following :
In a system, if virtual address = 32 bits, physical address = 24 bits, and the page size is 8KB.
Now we need to calculate the number of entries in the page table , my answer is as follows :
Here the page size is 8kB meaning that the offset is 13 ( 2^13=8K) , so now we have the logical address is 32 bits meaning that the page offset bits are 32-13=19, so therefore the page table will have 2^19 entries . Is that right ?
That would be 2^32 / 2^13 = 2^19 entries indeed.
The following parameters apply to a system employing a 40-bit virtual address and
1G bytes of physical (main) memory. Word size is 64 bits (8 bytes). Addresses point
to bytes and are aligned on byte boundaries. We use the following notation for an i-bit
address: Ai-1...A2,A1,A0 where Ai-1 is the most significant bit of the address and A0
is the least significant bit of the address. The virtual address is denoted by V39-V0
and the physical address is denoted by P29-P0.
Page size: 64 K bytes
Page table: three-level page table
The virtual page number is split in 3 fields of 8 bits each.
Entries in all tables are 32 bits (4 bytes).
This is what I have found so far,
Since it is a 40 bit virtual address and the Page Size is 64kB (2^16), 16 bits are for offset and we subtract 16 from 40. The remaining 24 bits are for the Virtual Page Number (VPN). The VPN is split in 3 fields of 8 bits each. So we have a three level page table. Each table has 2^8 entries and the size of each table is 2^8 * 4 bytes = 1024 bytes.
From here how would we proceed and find the total amount of virtual memory covered by one entry of page tables at each level?
At the lowest level each entry points to a single page, so working out the amount of virtual memory is trivial, its the size of 1 page. At each of the higher level, one entry represents n entries in the lower table (2^8 in this case). So for the second level its n * amount covered by a bottom level entry, or 2^8* the size of a page. Then use the size of a second level to repeat this calculation for the third level.
"The address consists of 16 bits, and the page size is 8KB. The page table thus consists of eight entries that are kept in fast registers."
How do we get the total entries in the page table as 8?
According to the calculation it should be 1.
Total Entries in the Page Table= ((2^16)/(2^3*2^10*2^3))=1.
(The first 2^3 is for 8 in 8KB, the second one is for bytes to bits conversion and 2^10 is for "Kilo" in 8KB.)
Thanks
Memory is byte-addressable hence, you do not need to divide by 2^3 for bytes to bit conversion.
Explaining it further, 16-bits for address means that the processor will generate memory addresses of length 16 bits which will be used to address the byte or half-word or word present starting (or ending - depends on the endianess of the machine) at that 16-bit value.
Now, the page size is the total size of a page in bits which in this case is 2^16 bits. But as memory is byte addressable, hence number of processor addresses in one page will be 2^16/2^3 i.e 2^13 addresses.
Hence number of page table entries are 2^16/2^13 = 8.
I'm writing an address translator for my operating system class. I know i'm reading in the virtual address correctly, and that the page number i get is correct (i access the right data) but when i try to figure out what the physical address is I get the wrong physical address.
specs:
2^8 entries in the page table
Page size = 2^8 bytes
Frame size = 2^8 bytes
256 frames
Physical memory = 65,536 bytes (256 frames × 256-byte frame size)
Here's a correct output:
Virtual address: 12107 Physical address: 2635 Value: -46
Here's what i'm getting:
Virtual address: 12107 Physical address: 12107 Value: -46
from my understanding the physical address is equal to (pageNumber * pageSize + pageOffset) everything i have read has said this.
When i get the page number from 12107, i get 47 (left most 8 bits)
When i get the offset from 12107, i get 75 (right most 8 bits)
(47 * 256 + 75) gets me 12107.
to get the correct output (physical address) the page number needs to be 10
(10 * 256 + 75) gets the correct output 2635.
I have poured over my book and have spent the last few days trying to find out where the heck i've gone wrong but i can't seem to figure it out.
I figured out what was happening, I had a misunderstanding in my implementation of page tables. I had a page table but no frame table it would be pointing to, the page table was actually completely bypassing that step, so in effect my physical and logical address were the same.
Once i implemented a frame table, and a proper method for populating the frame table i began generating the physical address correctly.
I'm looking over some exam papers for Operating Systems and I have come across a question which I simply cannot figure out. The memory management scheme is paging
Here is the question:
An operating system that runs on a CPU with a 16 bit address pointer employs a paging memory management scheme with a page size of 1024 bytes.
a) At most how many frames can physical memory contain?
b) Indicate which bits in an address pointer are used for page and offset.
c) A process image of size 3.5K resides in memory. You are given the page table of this process in Figure 1 below. What physical address will the hexadecimal logical address 0x0FCE result in? Show your calculations.
d) How much internal fragmentation does this process produce?
Page Frame
0 4
1 8
2 9
3 6
Figure 1 Process Page Table
Can anybody help me with this ?
A 16bit address bus allows to access 2^16 = 64kB of physical memory. Since on this system you have pages of size 1024B = 2^10, your memory falls into 2^16 / 2^10 = 2^6 physical frames.
Given the previous result, with pages of 1024 = 2^10 bytes, you need 10 bits for accessing any bytes of the page. Thus, the 6 high-order bits ares used for getting the page index from the page table (basically the figure 1 in your homework), and the 10 low-order bits are used for offsetting in that page.
The logical address 0xfce resides in the fourth page because the six high-order bits are 000011b = 3 = 4th page = 0x0c00-0x0fff. Given the page table and assuming the physical memory is sequential, the fourth page maps to the sixth physical frame which start at 1024 * 6 = 0x1800 = 0001100000000000b. The six high-order bits of the page are 000110b, where we add the 10 bits of offset resulting from the previous answer: 000110b << 10 | 0x3ce = 0x1bce.
Since the frame allocation is not sequential (4, 6, 8, 9), the hole between pages 4 and 6 (i.e. 1024B), and the hole between page 6 and 8(i.e. again 1024B), result in physical memory fragmentation.
Hope this help.