x86-64

x86-64

SSE instruction to interleave top 16-bits of packed 32-bit blocks of two XMM registers?

Disconected session Rad Studio XE2

How to decide if FF instruction is a call instruction or a jmp instruction in X86-64 ELF under linux? [duplicate]

Calculating jmp's from one segment to another in windows PE files

How to read memory with segment addressing mode in lldb on x86-64?

(x64) Where can I find CPU instructions usage statistics in contemporary programs?

Qbs support on MacOS with M1

Memory throughput for strided memory accesses

Unaligned access performance on Intel x86 vs AMD x86 CPUs

Nibble shuffling with x64 SIMD

knowing info about cpu while developing kernel

Can't set the higher half of ymm registers

EPT violations through speculative execution [duplicate]

Buffer overflow a simple echo program

For black-box analysis of the outcome of a system call, is a complete comparison of before-and-after forensic system images the right way to measure?

Can user code create a new memory segment?

INTEL X86，why do align access and non-align access have same performance?

Different structures in out of order processors

how to fix the problem while cpu store buffer cause data unconsistency?

Globally Invisible load & store memory operations

Usage of %line directive in NASM with dwarf debug format does not result in expected line numbers

What happens to a program that contains certain instructions that are not supported by the cpu in question?

What is the right way to determine, in CGo, if the environment supports AVX-512?

AVX512 or AVX2 vector permutations, group uint16 elements by strides of 16 (32 bytes)

Is the x86_64 architecture continuously being updated?

Why 16-byte alignment for `long double`?

AVX512 compare to vector not to mask

Construct a 64 bit mask register from four 16 bit ones

getting illegal instructions when vectorized code writes to PCI

_mm256_packs_epi32, except pack sequentially

How can I process the header of an exe when disassembling with iced_x86?

896-bit integer? Or 16384-bit? [duplicate]

Do these Windows executable meta data traits mean what I think they do?

Why does a loop transitioning from having its uops fed by the Uop Cache to LSD cause a spike in branch-misses?

What is the latency of `clwb` and `ntstore` on Intel's Optane Persistent Memory?

Why am I seeing more RFO (Read For Ownership) requests using REP MOVSB than with vmovdqa

Is UEFI required to map 4k pages on x64?

PMC to count if software prefetch hit L1 cache

Understanding factors in latency bounded memcpy/memset x86_64

Is it possible to run 64bit code on 32bit OS with 64-bit processor?

How can I multiply two vectors in NASM x86 assembly?

Do cache block replacement policies in x86 prefer clean blocks over dirty blocks?

signed avx512 vnni multiplication

Can the AMD64 ISA work without licensing the x86 ISA? [closed]

What is #object in **ELF**

How can I find the node6

Why does cmp instruction cost too much time?

8 Bit LERP with SSE

References memory at 0xFFFFFFFFFFFFFFFF

Can not compile wine on Centos 7 with 64

ghidra errors when trying to open ELF file

Bottleneck when using indexed addressing modes

Faster way to do _mm256_set1_ps

Get a negative result out of sub instruction x86_64

Atomicity of small PCIE TLP writes

Emulate AVX512 VPCOMPESSB byte packing without AVX512_VBMI2

GDTR and Segmentation in x86_64

64bit Hello world freezes after compiling

(.text+0x4e): undefined reference to `printf' nasm

How to emulate *really simple* variable bit shifts with SSE?

page:1 of 3 next page main page

Categories

azure-media-services

hyperledger-chaincode

atlassian-forge

database-schema

google-cloud-dataprep

sap-cloud-platform

arrow-functions

react-apollo-hooks

enterprise-library

connection-refused

assembly-references

meteor-accounts

applicationmanager

intel-parallel-studio

jquery-mobile-panel

unobtrusive-javascript

sitemapprovider

compass-geolocation

Resources