In a MIPS processor, I/O address space 0xffff0000 to 0xffffffff is reserved for memory-mapped I/O. Assuming that an I/O device needs 3, 1, and 4 32-bit words for control, status and data registers respecitvely. How many I/O devices can be supported?
The correct answer is 2048, but I got 8192.
My thought process:
Subtract the two spaces to retrieve the amount of memory needed
ffffffff - ffff0000 = 0000ffff = 65535 bits = 2^16 - 1
Then divide by 32-bits and multiply by 8, but that is obviously wrong.
Can someone guide me through the steps to get the correct answer? Thank you
Each devices uses: (3+1+4) * 32 bits = 8 * 4 bytes = 32 bytes
The available memory area is in bytes, not bits : 2^16 = 65536 bytes
Thus, you have: 65536 bytes / 32 bytes = 2048.
So 2048 devices are supported.
Related
I'm learning the concept of directed mapped cache, but I don't get it how to get cache memory size and main memory size by using block size. (The unit is bytes.) the given values are 2^3 words = 2^5 bytes of block size, 4 bits of tags(0000~1111) and 3 bits of the index(000~111).
the questions >>
what's the size of cache memory and main memory in each?
and which address do we insert in each data part?
I already tried to separate the part tag and the cache index. I insert the tag on 3 upper order bits and insert the cache index(29 bits) on the remaining space. I got the main memory size, 4GB, and the cache size, 2^29 bytes. but I think something is wrong. I feel that I don't understand the concept of this.
Your answer is incorrect, because you are assuming address is 32 bits and it is byte addressable, hence the 4GB memory size. This is not true and we must first compute these values.
8 words = 32 bytes = block size
So offset=3 bits (to address 8 words in a block)
and word size=4 bytes/word (32 bytes/8 words)
We have now the width of an address: 4 bits (tag) + 3 bits (index) + 3 bits (offset)= 10 bits.
With 10 bits address, main memory is 2^10 words=2^12 bytes=4kB
Cache has 8 blocks (3 bits index), each block has 32 bytes and cache size=8*32 bytes=256B.
It is said that 8086 Microprocessor has 1MB Memory and 20-bit address, 16- bit data bus . My doubt is that if it is 1MB memory that means (2^20 * 2^3) (1 byte = 8 bits) bits or 2^ 23 bits is the whole memory size. Then as 8086 is a 16- bit register then 2^20 ( from address lines) * 2^4( 16- bit size) is the memory i.e 2^ 24 bits which is not what I calculated above.
So there is a false in my assessment , what is that ?.
Each of the 2^20 addresses refers to an 8-bit Byte.
Some of the 8086's machine instructions operate on Bytes (8-bits) (using registers AH, AL, BH, BL, ...) and other machine instructions operate on Words (16-bits) (using registers AX, BX, ...).
When using a Word instruction, two adjacent bytes in memory (addresses (a) and (a+1)) are treated as a Word datum. I do not recall if the 8086 enforces even address alignment for Word-datum memory references. But, 2^20 Bytes contains only 2^19 Words (aligned to even addresses).
Bits are conserved:
(2^20 * 2^3) = (2^19 * 2^4) = 2^23
How would I convert a 16K x 32 SRAM into a 64K x 8 SRAM? The 16K x 32 RAM module is a single unit that cannot be altered internally and is capable of address decoding, has tristate outputs, and read/write/and chip enable. Also only the memory read of the circuit has to be implemented.
The 16K x 32 SRAM accepts a 14-bit address and produces a 32-bit value. However, the 64K x 8 SRAM accepts a 16-bit address and produces an 8-bit value. You can design a circuit whose interface exactly matches the interface of a 64K x 8 SRAM module. However, internally, it sends the most significant 14 bits of the supplied 16-bit address to the 16K x 32 SRAM together with the control signals. Then it uses the least significant 2 bits of the 16-bit address to select an 8-bit value from the 32-bit value produced by the 16K x 32 SRAM. Finally, the resulting 8-bit value is sent to the output pins of the circuit.
friend asked me a question about OS,in our computer,we can see it supports near 4G ROM if it is a 32-bit windows,he asked about the ROM 4g is bit or Byte,i said is Byte of course,but now i can not find out why is byte
4 G = 2^32 Bytes
1 Bytes = 8 bit
4 G = 2^35 bit
so why 32-bit system supports near 4 G ROM ..
i am not good at OS ..
2^32 = 4294967296 bytes(B)
= 4194304 KB
= 4096 MB
= 4 GB
= 34359738368 bits(b)
And why ROM ? I think you mean RAM. ROM is like burned data on an external support (called as CD or DVD)
You can burn as much as data you want on a CD or DVD, depending on its size, but windows in 32 bits can only assign 4294967296 addresses. Windows is also using this memory space so you should have 20% (on 4Gb RAM) which is reserved for Windows to run.
I've been reading through the horror that is the PCIe spec, and still can't get any kind of resolution to the following question pair.
Does PCIe allow for mapping huge (say 16GB) 64-bit non-prefetchable memory spaces up above the 4GB boundary? Or are they still bound to the same 1GB that they were in the 32-bit days, and there's just no way to call for giant swaths of non-prefetchable space?
Assuming that the spec allows for it (and to my reading it does), do widely available BIOSes support it? Or is it allowed in theory but not done in practice?
TL;DR / Short Answer
No. BAR requests for non-prefetchable memory are limited to using the low 32-bit address space.
http://www.pcisig.com/reflector/msg03550.html
Long Answer
The reason why the answer is no has to do with PCI internals. The data structure which describes the memory ranges that a PCI bus encompasses only reserves enough space to store 32-bit base and limit addresses for non-prefetchable memory and for I/O memory ranges. However, it does reserve enough space to store a 64-bit base and limit for prefetchable memory.
Even Longer Answer
Specifically, look at http://wiki.osdev.org/PCI#PCI_Device_Structure, Figure 3 (PCI-to-PCI bridge). This shows a PCI Configuration Space Header Type 0x01 (the header format for a PCI-to-PCI bridge). Notice that starting at register 1C in that table, there are:
1C: 8 (middle) bits for I/O base address. Only top 4 bits are usable.
1D: 8 (middle) bits for I/O limit address. Only top 4 bits are usable.
Ignore 1E-1F.
20: 16 bits for non-prefetchable memory base address. Only top 12 bits are usable.
22: 16 bits for non-prefetchable memory limit address. Only top 12 bits are usable.
24: 16 (middle) bits for prefetchable memory base address
26: 16 (middle) bits for prefetchable memory limit address
28: 32 upper bits for extended prefetchable memory base address
2C: 32 upper bits for extended prefetchable memory limit address
30: 16 upper bits for extended I/O base address
32: 16 upper bits for extended I/O limit address
The actual addresses are created by concatenating (parts of) these registers together with either 0s (for base addresses) or 1's (for limit addresses). The I/O and non-prefetchable base and limit addresses are 32-bits and formed thus:
Bit# 31 20 19 16 15 0
I/O Base: [ 16 upper bits : 4 middle bits : 12 zeros ]
I/O Limit: [ 16 upper bits : 4 middle bits : 12 ones ]
Non-prefetchable Base: [ 12 bits : 20 zeros ]
Non-prefetchable Limit: [ 12 bits : 20 ones ]
The prefetchable base and limit addresses are 64-bit and formed thus:
Prefetchable Base:
Bit# 63 32
[ 32 upper bits ]
[ 12 middle bits : 20 zeros ]
Bit# 31 16 15 0
Prefetchable Limit:
Bit# 63 32
[ 32 upper bits ]
[ 12 middle bits : 20 ones ]
Bit# 31 16 15 0
As you can see, only the prefetchable memory base and limit registers are given enough bits to express a 64-bit address. All the other ones are limited to only 32.
PCIe can define 64b memory addressing.
The BARs (Base Address Registers) definition and usage is defined in the PCI 3.0 spec (chapter 6.2.5.1 "Address Maps") not in the PCIe spec.