I'm learning the concept of directed mapped cache, but I don't get it how to get cache memory size and main memory size by using block size. (The unit is bytes.) the given values are 2^3 words = 2^5 bytes of block size, 4 bits of tags(0000~1111) and 3 bits of the index(000~111).
the questions >>
what's the size of cache memory and main memory in each?
and which address do we insert in each data part?
I already tried to separate the part tag and the cache index. I insert the tag on 3 upper order bits and insert the cache index(29 bits) on the remaining space. I got the main memory size, 4GB, and the cache size, 2^29 bytes. but I think something is wrong. I feel that I don't understand the concept of this.
Your answer is incorrect, because you are assuming address is 32 bits and it is byte addressable, hence the 4GB memory size. This is not true and we must first compute these values.
8 words = 32 bytes = block size
So offset=3 bits (to address 8 words in a block)
and word size=4 bytes/word (32 bytes/8 words)
We have now the width of an address: 4 bits (tag) + 3 bits (index) + 3 bits (offset)= 10 bits.
With 10 bits address, main memory is 2^10 words=2^12 bytes=4kB
Cache has 8 blocks (3 bits index), each block has 32 bytes and cache size=8*32 bytes=256B.
Related
Suppose we have a 64 bit processor with 8GB ram with frame size 1KB.
Now main memory size is 2^33 B
So number of frames is 2^33 / 2^10 which is 2^23 frames.
So we need 23 bits to uniquely identify every frame.
So the address split would be 23 | 10 where 10 bits are required to identify each byte in a frame (total 1024 bytes)
As it is word addressable with each word = 8B, will the address split now be 23 | 7 as we have 2^7 words in each frame?
Also can the data bus size be different than word size ?
If suppose data bus size is 128 bits then does it mean that we can address two words and transfer 2 words at a time in a single bus cycle but can only perform 64 bit operations?
Most of the answers are dependent on how the system is designed. Also there is bit more picture to your question.
There is something called available addressable space on a system. In a 32 bit application this would be 2^32 and in a 64 bit application this would be 2^64. This is called virtual memory. And there is physical memory which commonly refereed as RAM. If the application is built as 64 bits, then it is able work as if there is 2^64 memory is available. The underlying hardware may not have 2^64 RAM available, which taken care by the memory management unit. Basically it breaks both virtual memory and physical memory into pages( you have refereed to this as frames) and keeps the most frequently used pages in RAM. Rest are stored in the hard disk.
Now you state, the RAM is 8GB which supports 2^33 addressable locations. When you say the processor is 64 bits, I presume you are talking about a 64 bit system which supports 2^64 addressable locations. Now remember the applications is free to access any of these 2^64 locations. Number of pages available are 2^64/2^10 = 2^54. Now we need to know which virtual page is mapped to which physical page. There is a table called page table which has this information. So we take the first 54 bits of the address and index in to this table which will return the physical page number which will be 2^33/2^10 = 23 bits. We combine this 23 bits to the least 10 bits of the virtual address which gives us the physical address. In a general CPU, once the address is calculated, we don't just go an fetch it. First we check if its available in the cache, all the way down the hierarchy. If its not available a fetch request will be issued. When a cache issues a fetch request to main memory, it fetches an entire cache line (which is usually a few words)
I'm not sure what you mean by the following question.
As it is word addressable with each word = 8B, will the address split now be 23 | 7 as we have 2^7 words in each frame?
Memories are typically designed to be byte addressable. Therefore you'll need all the 33 bits to locate a byte within the page.
Also can the data bus size be different than word size ?
Yes you can design a data bus to have any width, but having it less than a byte would be painful.
If suppose data bus size is 128 bits then does it mean that we can
address two words and transfer 2 words at a time in a single bus cycle
but can only perform 64 bit operations?
Again the question is bit unclear, if the data but is 128 bits wide, and your cache line is wider than 128 bits, it'll take multiple cycles to return data as a response to a cache miss. You wont be doing operations on partial data in the cache (at least to the best of my knowledge), so you'll wait until the entire cache line is returned. And once its there, there is no restriction of what operations you can do on that line.
"The address consists of 16 bits, and the page size is 8KB. The page table thus consists of eight entries that are kept in fast registers."
How do we get the total entries in the page table as 8?
According to the calculation it should be 1.
Total Entries in the Page Table= ((2^16)/(2^3*2^10*2^3))=1.
(The first 2^3 is for 8 in 8KB, the second one is for bytes to bits conversion and 2^10 is for "Kilo" in 8KB.)
Thanks
Memory is byte-addressable hence, you do not need to divide by 2^3 for bytes to bit conversion.
Explaining it further, 16-bits for address means that the processor will generate memory addresses of length 16 bits which will be used to address the byte or half-word or word present starting (or ending - depends on the endianess of the machine) at that 16-bit value.
Now, the page size is the total size of a page in bits which in this case is 2^16 bits. But as memory is byte addressable, hence number of processor addresses in one page will be 2^16/2^3 i.e 2^13 addresses.
Hence number of page table entries are 2^16/2^13 = 8.
What does this statement mean with respect to an operating system?
With a 2^32 address space and 4K ( 2^12 ) page sizes, this leave 2^20
entries in the page table. At 4 bytes per entry, this amounts to a 4
MB page table, which is too large to reasonably keep in contiguous
memory. ( And to swap in and out of memory with each process switch. )
Note that with 4K pages, this would take 1024 pages just to hold the
page table!
Please explain how they are calculating 1024 pages at the end? What is 4 bytes per entry in this regard? What is the meaning of 4K page size? Does 4K mean 4*1024 bytes? Are they considering 4 bytes (per word) OR does 4 bytes means it has 4*1024 words with each word having some size, say 4 bytes?
Please explain to me how they are calculating 1024 pages at the end?
Remember that we're dealing with powers of two, so
4 MB = 4,194,304 Bytes
4 KB = 4096 Bytes
4 MB / 4 KB = 4,194,304 Bytes / 4096 Bytes = 1024 Bytes
What is 4 Bytes per entry in this regard?
You need 32 bits to reference all 2^32 address spaces. With 8 bits per Byte, 32 bits = 4 Bytes.
For example the first address is 0 and the last address is 4294967295 or (2^32 - 1).
Entry | Page Memory Location
------------------------------------------
1 | 0
2 | 4096
3 | 8192
... | ...
2^20 | 4294963200 -> (2^32 - 1) - 4096
Each entry in the table points to 1 page somewhere out in memory. In this example lets say it starts at zero. There will be 2^20 entries and they will cover the entire span of memory addresses (2^32). Since each entry is 4096 Bytes you only need 2^20 entries to cover all of the pages.
4K means 4*1024 bytes?
Yes, it refers to each page being 4096 bytes (4*1024).
Are they considering 4 bytes (per word), OR 4 bytes means it has 4*1024 words which each word having some size say 4 bytes?
It can be smaller on 32 bit processors, but normally a word is 32 bits or 4 Bytes.
Additions Comments
When I say a page size is 4K, then it means it has 1024 entries with 4 bytes each or 1024*4 entries with 1 byte each or what else?
The page can hold anything, it's a container of data that is, in this example, 4096 Bytes. The page table holds entries that point to pages. As David stated, since the page table is stored in memory, it also is stored in pages.
Someone was saying that explanation is wrong. Correct one is: With a 2^32 address space and 4K (2^12) page sizes, this leave 2^20 pages in the table. At 4 bytes per entry, this amounts to a 4 GB page table, which is too large to reasonably keep in contiguous memory. (And to swap in and out of memory with each process switch.) Note that with 4K page sizes, this would take 1024 k pages (=1M pages) just to hold the total table! Is he correct or wrong?
He is incorrect. If the page table actually contained the data from each page then he would be correct. With 4096 byte pages and 2^20 entries, that would equal 4,294,967,296 bytes (4 GB), but the entries are only 4 bytes in size. So you multiple that with 2^20 entries to get 4,194,304 bytes (4 MB).
The documentation assumes these values:
2^32 = number of bytes in address space
2^12 = 4K = 4*1024 = number of bytes in one page
2^20 = 1M = 1024*1024 = number of pages
4 = number of bytes in the page table to describe one page
4M = 4*1024*1024 = total number of bytes in the page table
1024 = (4*1024*1024)/(4*1024) = number of pages in the page table
So 4 bytes is 4 bytes (the size of the entry in the page table for one page,
not the size of the page itself!).
Yes, 4K means 4*1024 bytes, not 4*1024 words.
All memory in use by the OS and any applications is stored in pages somewhere on the system.
Since the page table is something that has to be stored in memory, it also is stored in pages.
I found this example.
Consider a system with a 32-bit logical address space. If the page
size in such a system is 4 KB (2^12), then a page table may consist of
up to 1 million entries (2^32/2^12). Assuming that
each entry consists of 4 bytes, each process may need up to 4 MB of physical address space for the page table alone.
What is the meaning of each entry consists of 4 bytes and why each process may need up to 4 MB of physical address space for the page table?
A page table is a table of conversions from virtual to physical addresses that the OS uses to artificially increase the total amount of main memory available in a system.
Physical memory is the actual bits located at addresses in memory (DRAM), while virtual memory is where the OS "lies" to processes by telling them where it's at, in order to do things like allow for 2^64 bits of address space, despite the fact that 2^32 bits is the most RAM normally used. (2^32 bits is 4 gigabytes, so 2^64 is 16 gb.)
Most default page table sizes are 4096 kb for each process, but the number of page table entries can increase if the process needs more process space. Page table sizes can also initially be allocated smaller or larger amounts or memory, it's just that 4 kb is usually the best size for most processes.
Note that a page table is a table of page entries. Both can have different sizes, but page table sizes are most commonly 4096 kb or 4 mb and page table size is increased by adding more entries.
As for why a PTE(page table entry) is 4 bytes:
Several answers say it's because the address space is 32 bits and the PTE needs 32 bits to hold the address.
But a PTE doesn't contain the complete address of a byte, only the physical page number. The rest of the bits contain flags or are left unused. It need not be 4 bytes exactly.
1) Because 4 bytes (32 bits) is exactly the right amount of space to hold any address in a 32-bit address space.
2) Because 1 million entries of 4 bytes each makes 4MB.
Your first doubt is in the line, "Each entry in the Page Table Entry, also called PTE, consists of 4 bytes". To understand this, first let's discuss what does page table contain?", Answer will be PTEs. So,this 4 bytes is the size of each PTE which consist of virtual address, offset,( And maybe 1-2 other fields if are required/desired)
So, now you know what page table contains, you can easily calculate the memory space it will take, that is: Total no. of PTEs times the size of a PTE.
Which will be: 1m * 4 bytes= 4MB
Hope this clears your doubt. :)
The page table entry is the number number of bits required to get any frame number . for example if you have a physical memory with 2^32 frames , then you would need 32 bits to represent it. These 32 bits are stored in the page table in 4 bytes(32/8) .
Now, since the number of pages are 1 million i.e. so the total size of the page table =
page table entry*number of pages
=4b*1million
=4mb.
hence, 4mb would be required to store store the table in the main memory(physical memory).
So, the entry refers to page table entry (PTE). The data stored in each entry is the physical memory address (PFN). The underlying assumption here is the physical memory also uses a 32-bit address space. Therefore, PTE will be at least 4 bytes (4 * 8 = 32 bits).
In a 32-bit system with memory page size of 4KB (2^2 * 2^10 B), the maximum number of pages a process could have will be 2^(32-12) = 1M. Each process thinks it has access to all physical memory. In order to translate all 1M virtual memory addresses to physical memory addresses, a process may need to store 1 M PTEs, that is 4MB.
Honestly a bit new to this myself, but to keep things short it looks like 4MB comes from the fact that there are 1 million entries (each PTE stores a physical page number, assuming it exists); therefore, 1 million PTE's, which is 2^20 = 1MB. 1MB * 4 Bytes = 4MB, so each process will require that for their page tables.
size of a page table entry depends upon the number of frames in the physical memory, since this text is from "OPERATING SYSTEM CONCEPTS by GALVIN" it is assumed here that number of pages and frames are same, so assuming the same, we find the number of pages/frames which comes out to be 2^20, since page table only stores the frame number of the respective page, so each page table entry has to be of atleast 20 bits to map 2^20 frame numbers with pages, here 4 byte is taken i.e 32 bits, because they are using the upper limit, since page table not only stores the frame numbers, but it also stores additional bits for protection and security, for eg. valid and invalid bit is also stored in the page table, so to map pages with frames we need only 20 bits, the rest are extra bits to store protection and security information.
I'm looking over some exam papers for Operating Systems and I have come across a question which I simply cannot figure out. The memory management scheme is paging
Here is the question:
An operating system that runs on a CPU with a 16 bit address pointer employs a paging memory management scheme with a page size of 1024 bytes.
a) At most how many frames can physical memory contain?
b) Indicate which bits in an address pointer are used for page and offset.
c) A process image of size 3.5K resides in memory. You are given the page table of this process in Figure 1 below. What physical address will the hexadecimal logical address 0x0FCE result in? Show your calculations.
d) How much internal fragmentation does this process produce?
Page Frame
0 4
1 8
2 9
3 6
Figure 1 Process Page Table
Can anybody help me with this ?
A 16bit address bus allows to access 2^16 = 64kB of physical memory. Since on this system you have pages of size 1024B = 2^10, your memory falls into 2^16 / 2^10 = 2^6 physical frames.
Given the previous result, with pages of 1024 = 2^10 bytes, you need 10 bits for accessing any bytes of the page. Thus, the 6 high-order bits ares used for getting the page index from the page table (basically the figure 1 in your homework), and the 10 low-order bits are used for offsetting in that page.
The logical address 0xfce resides in the fourth page because the six high-order bits are 000011b = 3 = 4th page = 0x0c00-0x0fff. Given the page table and assuming the physical memory is sequential, the fourth page maps to the sixth physical frame which start at 1024 * 6 = 0x1800 = 0001100000000000b. The six high-order bits of the page are 000110b, where we add the 10 bits of offset resulting from the previous answer: 000110b << 10 | 0x3ce = 0x1bce.
Since the frame allocation is not sequential (4, 6, 8, 9), the hole between pages 4 and 6 (i.e. 1024B), and the hole between page 6 and 8(i.e. again 1024B), result in physical memory fragmentation.
Hope this help.