I need to get current perl thread id in a C function inside *.XS part of a perl module.
In pure perl (*.pm part) I would simply do:
$id = threads->tid();
But what is a recommended way to get this value in XS?
Unfortunately http://perldoc.perl.org/perlthrtut.html and http://perldoc.perl.org/threads.html do not talk about dealing with threads in XS.
Thanks in advance
--
kmx
To call a method, one uses call_method.
UV get_tid() {
dSP;
UV tid;
ENTER;
SAVETMPS;
PUSHMARK(SP);
XPUSHs(sv_2mortal(newSVpv("threads", 0)));
PUTBACK;
count = call_method("tid", G_SCALAR|G_EVAL);
SPAGAIN;
if (SvTRUE(ERRSV) || count != 1)
tid = 0;
else
tid = (UV)POPi;
PUTBACK;
FREETMPS;
LEAVE;
return tid;
}
See how threads itself does it! I suggest you download threads from CPAN, unpack it and take a look at threads.xs. The part you need is a function called ithread_tid.
Related
My codes for Alu and Mux:
module alu(input logic [31:0]srca, srcb,
input logic [2:0] alucontrol,
output logic zero,
output logic [31:0]aluout);
logic [31:0] addr, subr, sltr, Andr, Orr;
assign addr = srca + srcb;
assign subr = srca - srcb;
assign sltr = (srca < srcb) ? 1 : 0;
assign Andr = srca & srcb;
assign Orr = srca | srcb;
always_comb
begin
case(alucontrol)
3'b010: aluout = addr;
3'b110: aluout = subr;
3'b111: aluout = sltr;
3'b000: aluout = Andr;
3'b001: aluout = Orr;
default: aluout = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
endcase
zero = (subr == 0) ? 1 : 0;
end
endmodule
module mux2#(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
always_comb
begin
y = s?d1 : d0;
end
endmodule
and their instantiation under the same top module:
alu alu(srca, srcb, alucontrol, aluout, zero);
mux2 #(32) resmux(aluout, readdata, memtoreg, result);
When I try to connect my 2-1Mux resmux with my alu, the aluout doesn't get connected to resmux
aluout gets suspended
I could solve this by exchanging the order of aluout and zero, but could anybody explain why this happens and how to avoid? Thanks a lot!
There are a number of mechanisms for connecting ports in SystemVerilog. The mechanism you are using is positional. That means each signal connection has to go in the prescribed order that they appear in the module declaration of alu. The way your code is written, the signal zero in module top is connected to last port aluout declared in module alu.
SystemVerilog also has a by_name syntax .portname(signal). You can list all your port connections in any order that way.
alu alu(.srca(srca), .srcb(srcb), .alucontrol(alucontrol), .alu(aluout), .zero(zero));
When the signal name you are connecting matches the declared port name, you can just use .portname.
alu alu(.alucontrol, .aluout, .zero, .srca, .srcb);
And finally, if all the port names match the signal names, you can use a wildcard, .* as well as list exceptions explicitly
alu alu(.*, .zero(my_zero));
I've written a couple production BPF agents, but my approach is very iterative until I please the verifier and can move on. I've reached my limit again.
Here's a program that works if I have one fewer && condition -- and breaks otherwise. The confusing part is that the warning implies that 103 insns is greater-than at most 4096 insns. There's obviously something I'm misunderstanding about how this is all strung together.
My ultimate goal is to do logging based on a process' environment -- so alternative approaches are welcome. :)
Error:
$ sudo python foo.py
bpf: Argument list too long. Program too large (103 insns), at most 4096 insns
Failed to load BPF program b'tracepoint__sched__sched_process_exec': Argument list too long
BPF Source:
#include <linux/mm_types.h>
#include <linux/sched.h>
#include <linux/version.h>
int tracepoint__sched__sched_process_exec(
struct tracepoint__sched__sched_process_exec* args
) {
struct task_struct* task = (typeof(task))bpf_get_current_task();
const struct mm_struct* mm = task->mm;
unsigned long env_start = mm->env_start;
unsigned long env_end = mm->env_end;
// Read up to 512 environment variables -- only way I could find to "limit"
// the loop to satisfy the verifier.
char var[12];
for (int n = 0; n < 512; n++) {
int result = bpf_probe_read_str(&var, sizeof var, (void*)env_start);
if (result <= 0) {
break;
}
env_start += result;
if (
var[0] == 'H' &&
var[1] == 'I' &&
var[2] == 'S' &&
var[3] == 'T' &&
var[4] == 'S' &&
var[5] == 'I' &&
var[6] == 'Z' &&
var[7] == 'E'
) {
bpf_trace_printk("Got it: %s\n", var);
break;
}
}
return 0;
}
Basic loader program for reproducing:
#!/usr/bin/env python3
import sys
from bcc import BPF
if __name__ == '__main__':
source = open("./foo.c").read()
try:
BPF(text=source.encode("utf-8")).trace_print()
except Exception as e:
error = str(e)
sys.exit(error)
bpf: Argument list too long. Program too large (103 insns), at most 4096 insns
Looking at the error message, my guess would be that your program has 103 instructions and it's rejected because it's too complex. That is, the verifier gave up before analyzing all instructions on all paths.
On Linux 5.15 with a privileged user, the verifier gives up after reading 1 million instructions (the complexity limit). Since it has to analyze all paths through the program, a program with a small number of instructions can have a very high complexity. That's particularly the case when you have loops and many conditions, as is your case.
Why is the error message confusing? This error message is coming from libbpf.c:
if (ret < 0 && errno == E2BIG) {
fprintf(stderr,
"bpf: %s. Program %s too large (%u insns), at most %d insns\n\n",
strerror(errno), attr->name, insns_cnt, BPF_MAXINSNS);
return -1;
}
Since the bpf(2) syscall returns E2BIG both when the program is too large and when its complexity is too high, libbpf prints the same error message for both cases, always with at most 4096 instructions. I'm confident upstream would accept a patch to improve that error message.
Is it possible to pass around a mailbox types in SystemVerilog using normal module IO? Most of the book examples of mailbox only show them being used inside of SystemVerilog classes. For example, could I do the follow? Is it legal?
module driver(
output mailbox mb
);
mailbox mbx = new(2);
initial begin
for (int i=0; i < 5; i++) begin
#1 mbx.put(i);
$display ("[%0t] Put #%0d, size=%0d",
$time, i, mbx.num());
end
end
endmodule
module sink(
input mailbox mb
);
initial begin
forever begin
int idx;
#2 mbx.get (idx);
$display ("[%0t] Got item #%0d, size=%0d",
$time, idx, mbx.num());
end
end
endmodule
module top;
mailbox mbx;
source(mbx);
sink(mbx);
endmodule
Yes, but your code has many errors. You were mixing up mb and mbx, and your module top was incorrect. Also, I strongly recommend using a parameterized mailbox to make is strongly typed. You'll thank me later when using many mailboxes. The following works for me
typedef mailbox#(int) i_mailbox;
module source(
output i_mailbox mbx
);
initial begin
mbx = new(2);
for (int i=0; i < 5; i++) begin
#1 mbx.put(i);
$display ("[%0t] Put #%0d, size=%0d",
$time, i, mbx.num());
end
#100 $finish;
end
endmodule
module sink(
input i_mailbox mbx
);
initial begin
forever begin
int idx;
#2 mbx.get (idx);
$display ("[%0t] Got item #%0d, size=%0d",
$time, idx, mbx.num());
end
end
endmodule
module top;
i_mailbox mbx;
source so(mbx);
sink si(mbx);
endmodule
I have the following code in my monitor:
virtual task run_phase(uvm_phase phase);
fork
begin : clock_c
forever begin
wait(vif.fact_log2_samp != fact_log2_samp_init);
for(int counter = 0; counter < 46; counter++) begin
check = 1'b0;
#(posedge vif.clk);
end
**check =1'b1;**
end// forever
end// clock_c
begin : main_0
forever begin
mon_trx = tx_lin_int_transaction::type_id::create("mon_trx");
mon_trx.fact_log_2 = fact_log2_samp_init;
**wait (vif.xn_valid == 1'b1);**
#1;
mon_trx.rand_data_xi = vif.xi;
mon_trx.rand_data_xq = vif.xq;
if (check == 1'b0)
mon_trx.check = FALSE;
else
fact_log2_samp_init = vif.fact_log2_samp;
$cast(t, mon_trx.clone());
//send transaction to scoreboard via TLM write()
ap.write(t);
wait (vif.xn_valid == 1'b0);
end// forever
end// main_0
join
endtask: run_phase
The problem is that
wait(vif.xn_valid == 1'b1);
and the code after it execute just before
check =1'b1;
(same time).
How can I ensure that the
check =1'b1;
will execute before?
I would follow the named events method, as AndresM suggested, but if you need a quick sync in the very same block with the very same trigger condition, a simple #0 might solve the issue, thou it is unreliable due to the simulation time handling reasons. Might worth a try:
begin : clock_c
...
**check =1'b1;**
...
end
begin : main_0
...
#0;
**wait (vif.xn_valid == 1'b1);**
...
end
also you can use labels for the begin-end blocks to look and read better, eg.:
begin: main_0, end: main_0 instead of end // main_o
You might want to take a look at Chapter 15 of the IEEE Std 1800-2012, where they cover in great detail every aspect related to the different interprocess synchronization and communication mechanisms that the SystemVerilog language offers. Those options are listed below (follow the hyperlinks to see a few examples and how to use each one of them):
Semaphores
Mailboxes
Named Events
My tests are in SystemC env and for all my tests i run a common routine(basically its my init sequence which doesn't vary much based on seed). This common routine is followed by my actual test.
It looks something like this:
Test_MAIN
init_seq();
my_test();;
Here init_seq() is that common routine and my_test() is my actual test that have actual test sequence which initiate multiple SC threads, for initiating various kind of traffic.
Now, my problem is that i want a way to avoid init_seq() for every run. The entire test should run for one time and the next time i should have a mechanism to directly run from my_test()(which is basically skipping/preloading init_seq() part to the simulator).
VCS save and restore can't be used directly as in this case we also will have to restore the SystemC variables.
Could you please direct me on this..!!
Thanks
ByreddyNaresh
I tried with a SystemC test with init() and run() routine, and use VCS save/restart to restore the test. It seems OK to me that a member variable 'cnt' in test is restored successfully.
This is my test:
// test.h
#ifndef TEST_H
#define TEST_H
#include <systemc.h>
class test: public sc_module{
public:
sc_in<bool> init_start;
sc_in<bool> run_start;
void init();
void run();
int cnt;
SC_CTOR(test){
SC_THREAD(init);
sensitive_pos << init_start;
dont_initialize();
SC_THREAD(run);
sensitive_pos << run_start;
dont_initialize();
}
};
#endif
and
// test.cpp
#include "test.h"
void test::init(){
printf("test init:\n");
while(1){
cnt = 10;
printf("init cnt to %d\n", cnt);
wait();
}
}
void test::run(){
printf("test run:\n");
while(1){
cnt++;
printf("cnt = %d\n", cnt);
wait();
}
}
and the top:
// tb.v
module tb;
reg init_start;
reg run_start;
initial begin
init_start = 0;
run_start = 0;
#100
init_start = 1;
#100
$save("save.chk");
#100
run_start = 1;
#100
$finish;
end
test u_test(
.init_start(init_start),
.run_start(run_start)
);
endmodule
After 'save.chk' is generated, I run it directly and the output is:
$ save.chk
Chronologic VCS simulator copyright 1991-2012
Contains Synopsys proprietary information.
Compiler version G-2012.09; Runtime version G-2012.09; Mar 5 18:01 2014
test run:
cnt = 11
$finish called from file "tb.v", line 17.
$finish at simulation time 1300
V C S S i m u l a t i o n R e p o r t
Time: 1300 ps
CPU Time: 0.260 seconds; Data structure size: 0.0Mb
Wed Mar 5 18:01:08 2014
It seems variable 'cnt' is restored from '10', as is done in init() routine.
Don't know if this is the case you met?