System Verilog- How to ensure that specific code will be executed before another? - system-verilog

I have the following code in my monitor:
virtual task run_phase(uvm_phase phase);
fork
begin : clock_c
forever begin
wait(vif.fact_log2_samp != fact_log2_samp_init);
for(int counter = 0; counter < 46; counter++) begin
check = 1'b0;
#(posedge vif.clk);
end
**check =1'b1;**
end// forever
end// clock_c
begin : main_0
forever begin
mon_trx = tx_lin_int_transaction::type_id::create("mon_trx");
mon_trx.fact_log_2 = fact_log2_samp_init;
**wait (vif.xn_valid == 1'b1);**
#1;
mon_trx.rand_data_xi = vif.xi;
mon_trx.rand_data_xq = vif.xq;
if (check == 1'b0)
mon_trx.check = FALSE;
else
fact_log2_samp_init = vif.fact_log2_samp;
$cast(t, mon_trx.clone());
//send transaction to scoreboard via TLM write()
ap.write(t);
wait (vif.xn_valid == 1'b0);
end// forever
end// main_0
join
endtask: run_phase
The problem is that
wait(vif.xn_valid == 1'b1);
and the code after it execute just before
check =1'b1;
(same time).
How can I ensure that the
check =1'b1;
will execute before?

I would follow the named events method, as AndresM suggested, but if you need a quick sync in the very same block with the very same trigger condition, a simple #0 might solve the issue, thou it is unreliable due to the simulation time handling reasons. Might worth a try:
begin : clock_c
...
**check =1'b1;**
...
end
begin : main_0
...
#0;
**wait (vif.xn_valid == 1'b1);**
...
end
also you can use labels for the begin-end blocks to look and read better, eg.:
begin: main_0, end: main_0 instead of end // main_o

You might want to take a look at Chapter 15 of the IEEE Std 1800-2012, where they cover in great detail every aspect related to the different interprocess synchronization and communication mechanisms that the SystemVerilog language offers. Those options are listed below (follow the hyperlinks to see a few examples and how to use each one of them):
Semaphores
Mailboxes
Named Events

Related

interrupt a TCP-IP callback function in matlab

Recently wrote code that establishes a connection between two instances of matlab. I can send messages through the TCP-IP connection which will execute code. Now I'm trying to setup the code to be interruptible as I would like to start/stop a function through TCP-IP. Problem though is that sending a second command does nothing until the function is completed. Is there a way to interrupt a TCP-IP callback function?
code:
classdef connectcompstogether<handle
properties
serverIP
clientIP
tcpipServer
tcpipClient
Port = 4000;
bsize = 8;
earlystop
end
methods
function gh = connectcompstogether(~)
% gh.serverIP = '127.0.0.1';
gh.serverIP = 'localhost';
gh.clientIP = '0.0.0.0';
end
function SetupServer(gh)
gh.tcpipServer = tcpip(gh.clientIP,gh.Port,'NetworkRole','Server');
set(gh.tcpipServer,'OutputBufferSize',gh.bsize);
fopen(gh.tcpipServer);
display('Established Connection')
end
function SetupClient(gh)
gh.tcpipClient = tcpip(gh.serverIP,gh.Port,'NetworkRole','Client');
set(gh.tcpipClient, 'InputBufferSize',gh.bsize);
set(gh.tcpipClient, 'BytesAvailableFcnCount',8);
set(gh.tcpipClient, 'BytesAvailableFcnMode','byte');
set(gh.tcpipClient, 'BytesAvailableFcn', #(h,e)gh.recmessage(h,e));
fopen(gh.tcpipClient);
display('Established Connection')
end
function CloseClient(gh)
fclose(gh.tcpipClient);
gh.tcpipClient = [];
end
end
methods
function sendmessage(gh,message)
fwrite(gh.tcpipServer,message,'double');
end
function recmessage(gh,h,e)
Message = fread(gh.tcpipClient,gh.bsize/8,'double');
if Message == 444
gh.Funwithnumbers();
elseif Message == 777
gh.earlystop = 1;
end
end
function Funwithnumbers(gh)
x=1;
while true
if x > 5000, break;end
if gh.earlystop == 1,break;end
x = x+1;
display(x)
end
end
end
end
for ease to understand code.
server
Ser = connectcompstogether;
ser.SetupServer();
ser.sendmessage(333);
Client
cli = connectcompstogether;
cli.SetupClient();
Update:
So after going through the web, I have found out based on this post that the tcpip callback cannot be interrupt. The post was in 2017 which means my 2016a version definitely cannot interrupt a callback.
So An update to my question, Is it possible to start a subprocess in matlab to run the function. I just want to use the callback to start code. If I can start a subprocess from the callback. Than I should be able to free up the main process and use tcpip to start/stop a function on a different computer.
Update 2:
So I tried to utilize parallel processing using the 'spmd' command but the problem still persisted.
function recmessage(gh,h,e)
Message = fread(gh.tcpipClient,gh.bsize/8,'double');
spmd
switch labindex
case 1
if Message == 444
gh.Funwithnumbers();
elseif Message == 777
gh.earlystop = 1;
end
end
end
end
You may use a timer object, which is convenient to delay the execution of some function.
t=timer('ExecutionMode','singleShot', 'StartDelay',0, 'TimerFcn',#myCallback);
start(t);
In this case, the StartDelay is 0, so myCallback will be almost immediately added to the queue of tasks to be processed by Matlab. The execution however will start only after the callback to the tcpip object has been completed. It will block the queue once started, however.
You may try something like:
properties
t=timer('ExecutionMode','singleShot', 'StartDelay',0, 'TimerFcn',#myCallback);
end
function tcpipCallback(gh,tcpObj,~)
message=fread(tcpObj,1,'double');
if message==444
if strcmp(get(t,'Running'),'on')
error('The function is running already');
else
set(gh.t,'UserData',false);
start(gh.t);
end
elseif message==777
set(gh.t,'UserData',true);
end
function myCallback(tObj,~)
ii=0;
while ii<5000
if get(tObj,'UserData'),break,end
ii=ii+1;
pause(.0001); %Pause to interrupt the callback; drawnnow might work too; or perhaps this is not needed at all.
end
end

Delays within tasks in system verilog

I am trying to call 4 tasks within another task as follows:
task execute();
logic [0:3] req1, port_select;
logic [0:3] req2;
logic [0:3] req3;
logic [0:3] req4;
logic [0:31] data11, data21;
logic [0:31] data12, data22;
logic [0:31] data13, data23;
logic [0:31] data14, data24;
bfm.reset_task();
//drive multiple ports
//repeat(1)
//begin: random_stimulus
port_select = generate_combination();
repeat(1)
begin: per_combination_iteration
//port1
req1 = port_select[0]? generate_command() : 0;
data11 = generate_data();
data21 = generate_data();
//bfm.drive_ip_port1(req,data1,data2);
//port2
req2 = port_select[1]? generate_command() : 0;
data12 = generate_data();
data22 = generate_data();
//bfm.drive_ip_port2(req,data1,data2);
//port3
req3 = port_select[2]? generate_command() : 0;
data13 = generate_data();
data23 = generate_data();
//bfm.drive_ip_port3(req,data1,data2);
//port4
req4 = port_select[3]? generate_command() : 0;
data14 = generate_data();
data24 = generate_data();
//bfm.drive_ip_port4(req,data1,data2);
fork
bfm.drive_ip_port1(req1,data11,data21);
bfm.drive_ip_port2(req2,data12,data22);
bfm.drive_ip_port3(req3,data13,data23);
bfm.drive_ip_port4(req4,data14,data24);
join
end: per_combination_iteration
//end: random_stimulus
$stop;
endtask: execute
And one of my drive_ip_port function is as follows:
//driving port2
task drive_ip_port2(input logic [0:3] req2, input logic [0:31] data1_port2, data2_port2);
req2_cmd_in = req2; //req2 command
req2_data_in = data1_port2; //req2 first operand
#200;
req2_cmd_in = 0;
req2_data_in = data2_port2; //req2 second operand
#1000;
endtask: drive_ip_port2
This is what I am trying to achieve:
I want the execute task to drive 4 ports randomly. On the first clock, I want them to send a command and data. And then on the next clock, the command should be 0 and only data need to be sent.
This is what I have tried:
As shown in my code, I have written the above code. The thought behind this code was that since tasks can handle time delays, I can call the task once and pass the data and the command and let task handle all the work.
The problem I have:
After the first clock period, I have a delay of #200(equal to my clock). Thereafter, the wire should become 0 and should remain 0 for #1000. However, I am never getting the value 0 on command. It looks like the command gets driven by this task again. I have tried using Local variables, using the watch feature, using breakpoint but still couldn't debug it. Can anyone suggest what's wrong?
I don't know why req2_cmd_in does not get set to zero. Maybe there is somewhere else an overriding assignment like a typo in another task. (Try call only one task and see what that does.)
I do know that if you want something to happen at or after a clock, wait for that clock, do not use a delay. Safest is also to make sure you start at a determined point from a clock edge. Therefore I prefer to use in my test-benches code like this:
task drive_ip_port2(input logic [0:3] req2,
input logic [0:31] data1_port2, data2_port2);
// Use this or make sure you call the task at a
// determined point from the clock
# (posedge clk) ;
// Signals here change as if they come from a clocked register
req2_cmd_in <= req2; //req2 command
req2_data_in <= data1_port2; //req2 first operand
# (posedge clk) ;
req2_cmd_in <= 0; // No command
req2_data_in <= data2_port2; // only req2 second operand
repeat (4) // 4 or 5 depends on if you wait for clock at top
# (posedge clk) ;
endtask: drive_ip_port2

How to get fork join/join_any to work with a loop

As per the SV LRM section 9.3.2
for(int j=1; j <=3; ++j)
fork
automatic int k = j;
begin
.... # use k here
end
join_none
this is how to create a fork in a loop. I have tried it and it works. But if i want to create fork with join and not join_none in loop it does not work as expected but works sequentially.
How can i modify this to work using a join, i want all my forks to fork off simultaneously and then wait for all of them to finish(join) or one of them to finish(join_any)?
Thanks
If you want to wait for all of the processes fork'ed by the fork-jone_none to complete, you put a wait fork; statement after the for loop. The wait fork statements waits for all child processes of the current thread to complete.
Id there are processes created by fork-jone_none before this for loop still active that you do not want to wait for, you need to put this piece of of code in an isolation thread.
fork
some_other_process;
join_none
fork
begin : isolation_process
for(int j=1; j <=3; ++j) begin : for_loop
fork
automatic int k = j;
begin
.... # use k here
end
join_none
end : for_loop
wait fork; // will not wait for some other process
end :isolation_thread
join
To get the behavior of the fork-join_any requires some handshaking signal or event in each process to signal that it is done.
event join_any_event;
for(int j=1; j <=3; ++j) begin : for_loop
fork
automatic int k = j;
begin
.... # use k here
->> join_any_event;
end
join_none
end : for_loop
#join_any_event;
you are looking for wait fork. See IEEE Std 1800-2012 ยง 9.6.1 Wait fork statement
The wait fork statement blocks process execution flow until all immediate child subprocesses (processes created by the current process, excluding their descendants) have completed their execution.
Add the wait fork after your for-loop to get the desired effect:
for(int j=1; j <=3; ++j)
fork
automatic int k = j;
begin
.... # use k here
end
join_none
wait fork; // wait for all the above fork-join_none to complete

The counter counts strangly

My code describes a FSM to control a traffic light. There are four states, each with a different
duration.
Whenever the counter equals 1, the counter needs one more clock to change to the next value. For example, at state1, counter is programmed to count from 4 to 1. Every value should only take one clock to
change to the next, when it does, the state is changed to the next state. But when counter equals 1, it takes two clocks to change.
My program is as follows. The counter is implemented at the bottom of the always block:
module HW3(times,A,B,clk,rst,iHand,iChang,s1);
input clk,rst;
output reg [2:0]A,B;
wire oclk;//new freq
reg [2:0] count1,count2,count3,count4;//count times
reg [2:0]times;
reg temp;//control the switch
parameter [2:0]state1=3'd0,state2=3'd1,state3=3'd2,state4=3'd3;
always#(posedge clk or negedge rst )
begin
if(!rst)
begin
s1<=state1;
A<=3'b0;
B<=3'b0;
count1<=3'd4;
count2<=3'd2;
count3<=3'd3;
count4<=3'd2;
temp<=1'b1;
end
else
begin
if(temp==1)
begin
temp<=1'b0;
case(s1)
state1:
begin
times<=count1;
A<=3'b001;
B<=3'b100;
s1<=state2;
end
state2:
begin
times<=count2;
A<=3'b010;
B<=3'b100;
s1<=state3;
end
state3:
begin
times<=count3;
A<=3'b100;
B<=3'b001;
s1<=state4;
end
state4:
begin
times<=count4;
A<=3'b100;
B<=3'b010;
s1<=state1;
end
default:
begin
A<=3'b000;
B<=3'b000;
end
endcase
end
else
begin
if(times>1)
times<=times-1;
else if(times==1)
begin
temp<=1'b1;//can't count averagely
end
end
end
end
endmodule
Modify the code at the bottom of the always clock as:
if(times>2)
times<=times-1;
else if(times==2)
begin
times=times-1;
temp<=1'b1;//can't count averagely
end
Just let the times counts to 2 ,because if let it count to 1, the program will again enter the if
block in the next clock but doesnt change the value of times ,and make the value of times=1 unchanged
for one more clock

[Verilog]Why my counter's output delays one more clock?

My partial program is as followed, it's a FSM to handle the traffic light,and the register "times" (from 4 to 1) is to compute the time that the traffic light should brighten, But whenever "times" counts to "1", the time of "times=1" is longer than other "times" about one clock.
For example:when times = 4~2,every clock will count ,but when times=1,it will take two clocks
to become times=4.
Could anybody tell me how this problem happened?
always#(posedge clk or negedge rst )
if(!rst)
begin
s1<=state1;
A<=3'b0;
B<=3'b0;
count1<=3'd4;
count2<=3'd2;
count3<=3'd3;
count4<=3'd2;
temp<=1'b1;
end
else
begin
if(temp==1)
begin
temp<=1'b0;
case(s1)
state1:
begin
times<=count1;
A<=3'b001;
B<=3'b100;
s1<=state2;
end
state2:
begin
times<=count2;
A<=3'b010;
B<=3'b100;
s1<=state3;
end
state3:
begin
times<=count3;
A<=3'b100;
B<=3'b001;
s1<=state4;
end
state4:
begin
times<=count4;
A<=3'b100;
B<=3'b010;
s1<=state1;
end
default:
begin
A[0]<=3'b000;
B[0]<=3'b000;
end
endcase
end
else
begin
if(times>1)
times<=times-1;
else if(times==1)
begin
temp<=1'b1;//can't count averagely
end
end
end