I have this assertion in order to check clk freq:
assert property clk_freq;
int cnt;
#(posedge fast_clk, clk_1MHz) disable_iff(!enable_check)
($rose(clk_1MHz), cnt=0) |=> (!$rose(clk_1MHz),cnt++) [*0:$] ##1 $rose(clk_1MHz), cnt==fast_clk_freq;
endproperty
fast_clk starts to toggle during (not from beginning) of the simulation after disable_check is asserted.
The problem is that it seems that the assertion ignores the disable_iff
Question: is a $rose(clk_1Mhz) event "registered" even though the assertion is disabled (or am I missing something else ?)
There is no disable_iff keywords, it is disable iff (without the underscore). Properties can have local variables but the local variables cannot be defined inline with assert. Separate the property definition and the assertion instantiation.
The clock sampling doesn't seem to be correct. #(posedge fast_clk, clk_1MHz) mean on rising fast_clk or any change to clk_1MHz. clk_1MHz is the sampled data value, therefore it should not be a clock.
$rose(clk_1MHz), cnt==fast_clk_freq is ilegal syntax, sugest: $rose(clk_1MHz) ##0 cnt==fast_clk_freq
Suggested property definition and the assertion instantiation:
property p_clk_freq;
int cnt;
#(posedge fast_clk) disable iff(!enable_check)
($rose(clk_1MHz), cnt=0) |=> (!$rose(clk_1MHz),cnt++)[*0:$] ##1 $rose(clk_1MHz) ##0 cnt==fast_clk_freq;
endproperty
a_clk_freq : assert property(p_clk_freq);
For more on assertions refer to section 16 of IEEE Std 1800-2012.
Related
I have to write system verilog assertion with binding.
The assertion should be something like:
assert property (#(posedge (mod_clk & clk_gen_enable)) ##delay (clk_sync == 1));
mod_clk, clk_gen_en and clk_sync are signal of the module which I bind to, and delay is a variable which is a result of a calculation and should be in "units" of st_clk which is also signal of the module which I bind t
How can I write it correctly??
For bind to work, all you need is encapsulate this assertion in a module
module my_module;
assert property (#(posedge (mod_clk & clk_gen_enable)) ##delay (clk_sync == 1));
endmodule
The use the bind construct to insert my_module into your target module. Verilog search rules will search upwards to find your signal names.
bind my_target_module my_module my_instance_name();
##delay works on the clock edge you specified before it which you have as mod_clk & clk_gen_enable. I'm guessing you really mean to have clk_gen_enable as an implication.
property sync;
int counter;
#(posedge mod_clk) (clk_gen_enable, counter=delay)
|-> #(posedge st_clk) (1,counter--)[*0:$] ##1 counter<0 ##0 (clk_sync == 1));
endproperty
Assume SV interface contains a concurrent assertion property.
Is it possible to enable this assertion only when an event is triggered? I tried writing property inside a task in interface file, but I ended up with error: near "property": syntax error, unexpected property.
Interface intf;
task e1();
-> e1;
endtask
wait(e1.triggered); // something like this, where property waits for trigger
property prop1;
#(posedge clk) a ##1 b;
endproperty
endinterface
Thank you.
I think you need to consider that properties are best written synchronously and are evaluated on every clock cycle. You property says that one cycle after every clock cycle where a occurs b occurs. I guess what you're after is something like:
if e1 occurs, then a should be true (on the next rising edge of
clk?) and then b should be true on the rising edge of clk after
that
So, one way of doing that would be to create an always block that generates a pulse one clock wide should e1 occur, eg:
always begin
#(e1);
#(posedge clk) e = 1'b1;
#(posedge clk) e = 1'b0;
end
property prop1;
#(posedge clk) e |-> a ##1 b;
endproperty
or some variation of that. I feel like I should be worried about races, however.
property prop1;
#(posedge clk)
$fell(sig1) ##1 sequence1 |-> sequence2;
endproperty
I want to disable the property iff sig1=1'b1 after first clock cycle.
Transition from high to low on sig1 is my triggering condition. If I do disable iff(sig1) triggering condition will not be met.
Also using throughout is not possible on both enabling and satisfying sequences in formal verifiers.
How can i do it?
Thanks!
How about writing some satellite code to derive a delayed version of sig:
always #(posedge clk) sig1d <= sig1;
property prop1;
#(posedge clk) disable iff(sig1d)
$fell(sig1) ##1 sequence1 |-> sequence2;
endproperty
http://www.edaplayground.com/x/2tbX
You can re-write your assertion to only trigger if you don't see sig1 high after the first cycle:
property prop1;
#(posedge clk) disable iff(sig1d)
$fell(sig1) ##1 !sig1 ##0 sequence1 |-> sequence2;
endproperty
I want to write a property in SVA to formally verify a behavior.
Here is what I want to:
property prop1(sig1,sig2,sig3,sig4);
#(posedge clk)
$fell(sig1) ##[1:$] first_match($fell(sig2)) ##0 sig3 |-> sig4 == sig3;
endproperty
How can I rewrite the above property so that after sig1 falls, it stays LOW during remaining Evaluation cycles?
Note: I do not want to put sig1 as disable iff (sig1)
property prop1(sig1,sig2,sig3,sig4);
#(posedge clk)
(!sig1) throughout (##[1:$] first_match($fell(sig2)) ##0 sig3)
|-> sig4 == sig3;
endproperty
See section 16.9.9 Conditions over sequences in the 1800-2012 LRM
I am trying to do something like this:
assert property (#(posedge clk) disable iff (!rst) a[*c] -> $rose(b))
Here c is not a 'constant' but a value coming from some bits of a register. eg: reg[4:0] which is written only once. The check is to see if b is asserted only when a is high for "c" number of cycles.
However, SVAs do not accept a variable like this : [*reg[4:0]]. Any ideas??
Introduce a local variable ctr. At every posedge a new assertion with a new instance of ctr will be created. Set ctr equal to the value in reg1. Check that a is true throughout the down count. Decrement the counter as long as it is larger than zero. The (ctr>0, ctr--)[*0:$] statement will count down until ctr == 0 is true.
You might want to change (ctr>0, ctr--)[*0:$] to (ctr>0, ctr--)[*1:$], depending on what results you expect if reg == 0.
property pr_aRegTimes;
integer ctr;
disable iff (!rst)
#(posedge clk)
(1, ctr = reg1) ##0 a throughout ((ctr>0, ctr--)[*0:$] ##1 (ctr == 0)) |-> $rose(b);
endproperty
as_aRegTimes: assert property (pr_aRegTimes)
else $error("aRegTimes failed");
Working example:
http://www.edaplayground.com/x/Xh9
Sources:
https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/
http://www.win.tue.nl/~jschmalt/teaching/2IMF20/SvaFvTutorialHVC2013.pdf
property pr_aRegTimes;
integer ctr;
disable iff (!rst)
#(posedge clk)
($rose(a), ctr = reg1) ##0 (a&&ctr>0,ctr--)[*] |-> $rose(b);
endproperty