I have to write system verilog assertion with binding.
The assertion should be something like:
assert property (#(posedge (mod_clk & clk_gen_enable)) ##delay (clk_sync == 1));
mod_clk, clk_gen_en and clk_sync are signal of the module which I bind to, and delay is a variable which is a result of a calculation and should be in "units" of st_clk which is also signal of the module which I bind t
How can I write it correctly??
For bind to work, all you need is encapsulate this assertion in a module
module my_module;
assert property (#(posedge (mod_clk & clk_gen_enable)) ##delay (clk_sync == 1));
endmodule
The use the bind construct to insert my_module into your target module. Verilog search rules will search upwards to find your signal names.
bind my_target_module my_module my_instance_name();
##delay works on the clock edge you specified before it which you have as mod_clk & clk_gen_enable. I'm guessing you really mean to have clk_gen_enable as an implication.
property sync;
int counter;
#(posedge mod_clk) (clk_gen_enable, counter=delay)
|-> #(posedge st_clk) (1,counter--)[*0:$] ##1 counter<0 ##0 (clk_sync == 1));
endproperty
Related
Assume SV interface contains a concurrent assertion property.
Is it possible to enable this assertion only when an event is triggered? I tried writing property inside a task in interface file, but I ended up with error: near "property": syntax error, unexpected property.
Interface intf;
task e1();
-> e1;
endtask
wait(e1.triggered); // something like this, where property waits for trigger
property prop1;
#(posedge clk) a ##1 b;
endproperty
endinterface
Thank you.
I think you need to consider that properties are best written synchronously and are evaluated on every clock cycle. You property says that one cycle after every clock cycle where a occurs b occurs. I guess what you're after is something like:
if e1 occurs, then a should be true (on the next rising edge of
clk?) and then b should be true on the rising edge of clk after
that
So, one way of doing that would be to create an always block that generates a pulse one clock wide should e1 occur, eg:
always begin
#(e1);
#(posedge clk) e = 1'b1;
#(posedge clk) e = 1'b0;
end
property prop1;
#(posedge clk) e |-> a ##1 b;
endproperty
or some variation of that. I feel like I should be worried about races, however.
I've trouble designing assertions(SVA) for this scenario.
When a mux sel is asserted, the data_in is expected to be stable for 2 clocks ; clock prior to mux sel being asserted, and the current clock when mux sel is asserted.
Now the data_in is a wide vector/bus signal, whereby some bits of the bus are Z and X during functional mode (this is expected), while this bits may carry value during non-functional mode.
This then implies, the approach to design the SVA would be to compare bit by bit of data bus when mux sel is asserted.
This is my approach, but SVA fails and am not sure why.
generate
for( genvar i=1 ; i<BUS_WIDTH ; i++ ) begin
always # (posedge clk) begin
if(!$isunknown(data_in[i]) && reset) begin
data_in_temp_prev[i] <= data_in[i];
if (mux_sel==1 && reset==1 && i>0) begin
SVA_TEST: assert property (data_in[i] == data_in_temp_prev[i-1]) else `uvm_error("TRIAL_SVA",$sformatf("datain expected to be stable for 2 clks prior to mux sel"));
end //if
end //if isunknown
else begin
din0_temp_prev[i] <= 0;
end
end //always
end // for genvar
endgenerate
Any suggestions on how to approach designing this SVA ?
Thanks.
If I understood correctly your problem, you don't need all this structure for this kind of problem, look at my example below and tell me if helps or not.
property mux_compare;
disable iff(!reset)
#(posedge mux_sel)
!$isunknown(data_in)
|->
#(posedge clk)
$stable(data_in) [*2];
endproperty: mux_compare
My approach to SVA checkers is to use a standard structure to properties to avoid all kinds of problems. the structure is to always use clocked properties with "disable iff" and always use an implication operator, where the left hand side is the trigger and the right hand side is what we want to verify.
Here's an example from the LRM:
property abc(a, b, c);
disable iff (c) #(posedge clk) a |=> b;
endproperty
similarly to the answer above, I would do this:
property mux_compare;
disable iff(!reset) #(posedge clk)
mux_sel===1 |->
!$isunknown(data_in[i]) || $stable(data_in) && data_in[i] == $past(data_in[i],2);
endproperty: mux_compare
I want to verify that if an event occurrs, then at “num_ticks” in the past, some signal should have been asserted.
As an example, the property I wrote is:
property test_past;
#(posedge clk)
$rose(gnt) |-> $past(req, num_ticks);
endproperty
The problem here is with num_ticks. If num_ticks is an input signal to the module in which the property is written, then the assertion fails. If I declare num_ticks as an int, and assign it to a constant, it passes.
Does $past only work for constant values? This is not mentioned in the LRM.
I am using Questasim 10.3
You might use multiple assertions for this purpose.
Suppose num_ticks is 4 bits wide, then you can do like this.
genvar x;
generate
for (x=0; x<16; x++)
begin
property test_past;
#(posedge clk)
(num_ticks == x) && $rose(gnt) |-> $past(req, x);
endproperty
end
endgenerate
I have this assertion in order to check clk freq:
assert property clk_freq;
int cnt;
#(posedge fast_clk, clk_1MHz) disable_iff(!enable_check)
($rose(clk_1MHz), cnt=0) |=> (!$rose(clk_1MHz),cnt++) [*0:$] ##1 $rose(clk_1MHz), cnt==fast_clk_freq;
endproperty
fast_clk starts to toggle during (not from beginning) of the simulation after disable_check is asserted.
The problem is that it seems that the assertion ignores the disable_iff
Question: is a $rose(clk_1Mhz) event "registered" even though the assertion is disabled (or am I missing something else ?)
There is no disable_iff keywords, it is disable iff (without the underscore). Properties can have local variables but the local variables cannot be defined inline with assert. Separate the property definition and the assertion instantiation.
The clock sampling doesn't seem to be correct. #(posedge fast_clk, clk_1MHz) mean on rising fast_clk or any change to clk_1MHz. clk_1MHz is the sampled data value, therefore it should not be a clock.
$rose(clk_1MHz), cnt==fast_clk_freq is ilegal syntax, sugest: $rose(clk_1MHz) ##0 cnt==fast_clk_freq
Suggested property definition and the assertion instantiation:
property p_clk_freq;
int cnt;
#(posedge fast_clk) disable iff(!enable_check)
($rose(clk_1MHz), cnt=0) |=> (!$rose(clk_1MHz),cnt++)[*0:$] ##1 $rose(clk_1MHz) ##0 cnt==fast_clk_freq;
endproperty
a_clk_freq : assert property(p_clk_freq);
For more on assertions refer to section 16 of IEEE Std 1800-2012.
SLV_DCR_TIMEOUT_WAIT is the value programmed in the register hence it is not a constant value. How can I use the same in assertion.
assign DCR_CLK = testbench.sw_top_inst.DUT.megatron_x.megatron_cib.dcr_slave_cfg.DCR_clk;
assign DCR_TIMEOUT_WAIT = testbench.sw_top_inst.DUT.megatron_x.megatron_cib.dcr_slave_cfg.dcr_timeout_wait[15:0];
assign SLV_DCR_TIMEOUT_WAIT = testbench.sw_top_inst.DUT.megatron_x.megatron_cib.dcr_slave_cfg.Sl_dcrTimeoutWait;
assign SCRUB_INIT = testbench.sw_top_inst.DUT.megatron_x.megatron_cib.dcr_slave_cfg.scrub_init;
// end
//=================ASSERTION TO CHECK SLV_DCR_TIMEOUT_WAIT============================//
property slv_dcr_timeout_wait;
#(posedge DCR_CLK) disable iff (!DCR_TIMEOUT_WAIT)
$rose(SCRUB_INIT) |-> $rose(SLV_DCR_TIMEOUT_WAIT) ##(DCR_TIMEOUT_WAIT) $fell(SLV_DCR_TIMEOUT_WAIT);
endproperty: slv_dcr_timeout_wait
assert property (slv_dcr_timeout_wait);
Error message :
Error-[SVA-INCE] Illegal use of non-constant expression
/lsi/designs/rsd_megatron/team/singhs/megatron/sim/testbench/mss_tb/interfaces/mss_internal_signal_if.sv, 41
mss_internal_signal_if, "DCR_TIMEOUT_WAIT"
The use of a non-constant expression is not allowed in properties, sequences
and assertions for cases such as delay and repetition ranges.
Please replace the offending expression by an elaboration-time constant.
As you noticed, the issue is with ##(DCR_TIMEOUT_WAIT), SystemVerilog want it to be a constant value. I use local variable counters to get around this. See IEEE Std 1800-2012 § 16.10 Local variables
Using a local variables create a generic pulse checking sequences:
sequence pulse_seq(local logic sig, local int limit);
int cnt = limit;
$rose(sig) ##0 (sig && cnt>0, cnt--)[*] ##1 ($fell(sig) && cnt==0);
endsequence
Then plug it into the assertion:
property slv_dcr_timeout_wait;
#(posedge DCR_CLK)
$rose(SCRUB_INIT) && (DCR_TIMEOUT_WAIT>0) |->
pulse_seq(SLV_DCR_TIMEOUT_WAIT,DCR_TIMEOUT_WAIT);
endproperty : slv_dcr_timeout_wait
assert property (slv_dcr_timeout_wait);
Note that I removed disable iff (!DCR_TIMEOUT_WAIT)and to the trigger I changed the trigger condition to $rose(SCRUB_INIT) && (DCR_TIMEOUT_WAIT>0). Disable is asynchronous action and should be used to abort a sequence that already started.
Proof of concept here (Note: Riviera-PRO EDU 2014.10 does not appear to properly support sequence port lists to I had to hard coded the signals. Should work in any full simulator that supports IEEE Std 1800-2005 or greater)