As the title suggests, I am having a problem trying to figure out how to combine 2x 16 bit into 1x 32 bit, can anyone point me in the right direction? Cheers in advance
From a mathematical standpoint you can do
32 bit word = (high word * 65536) + low word
Related
The image is relating to an example of translating in virtual memory. The address of phys. mem. starts from 0x000 ~ 0x0FC, then moves start 0x100 ~ 0x1FC and so on. Why don't it go like 0x000 ~ 0x0FF, and then 0x100 ~ 0x1FF etc. What are the two lowest bits stand for?
Thank you for your answers. This photo came from MIT open course, and they didn't reveal more details about the address. But I finally figured it out in the later example of the courses.
The two lowest bits can always be zero as the following example:
Supports that we have:
4GB of MM size.
64 lines of cache.
ONLY 1 WORD = 4 bytes PER CACHE LINE.
The address have 32 bits because of 4GB of MM.
The partial address defining the line have 6 bits because of 64 lines of cache.
And because the cache size is 2^6*4B
=> The tag have 24 bits (log2(4GB/2^8B))
=> The lowest bits have 2(32 - 24 - 6) bits.
Because there is only a word per block so that the lowest bits, which act as a data boundary(This is what the course said), are always 0.
I've just played around with SHA256, and I've noticed something weird: the length of the hexdigest is 32 chars, each can be one of 16 different characters (0-9, a-f). Now correct me if I'm wrong, but this is not 256. 16*32 makes 512.
So... what am I missing here? Why the extra 16 letters?
Thanks in advance for your help.
First of all, this is not really my answer, it was #kelaka that set me stright on the path to an answer in the comment - so I'm not getting to excited about myself.
I was trying to calculate the number of options wrong, but multiplying 16 and 64 (the real length of a hash). If I calculated it the way it should have been - 16 ^ 64, I'd get a large number that is equal to 2^256, as can be seen in this code here:
>>> 16**64 == 2**256
True
Sorry for wasting everyone's time on me being stupid.
could anyone please explain how does memory layout works on STM32, for example I am using STM32F205RCT6 which say it has 256Kbyte of FLASH.
If I understand it correctly it means I cannot use memory past Sector 5., because I would violate 256Kb size, is that correct?
Datasheet image below (link to datasheet)
You can access as much memory as you have.
If you have 256Kbyte flash you can access at 0x8000000 - 0x803FFFF
When you erase the sector you can only access Sector 0, Sector 1,Sector 2,Sector 3,Sector 4, Sector 5 as sum of sizes of those sectors is 256kbyte (rather simple math)
16 + 16 + 16 + 16 + 64 + 128 = 256
S0 + S1 + S2 + S3 + S5 + S5
You must understand that the datasheet is used for a large variety of models. The model that you are using have only 256KB, but other models have up to 1MB, that's why the datasheet shows so many sectors.
I'm revising for an exam and i've came across a question that I have no idea how to do, i've looked through my notes and cant seem to find anything on it, can anyone help me?
Given a 64KB cache that contains 1024 blocks with 64 bytes per block, what is the size of the tag field for a 32-bit architecture?
The question is only worth 1 mark so i cant imagine the answer is too hard, but i cant seem to find anthing on it.
You need 32 bits for the address. You need 6 bits for the offset within a block. You need 10 bits to identify one of the 1,024 possible blocks in the cache. That's 16 bits in total. Therefore the tag needs to be 32 bits - 16 bits = 16 bits.
I recommend following the link that aruisdante provided and look at how to calculate this yourself.
I have a doubt..range of a 32 bit register is 2^32 ..is it because a bit can store 2 values if yes please could you justify it..it's really confusing..
Say you have 2 bit. The possible different binary values you could create., with 2 bit is 00, 01,10, and 11 hence 2^2 = 4. Hence, for decimal you could store 0,1,2,3 (4 vlaues) with 2 bits.
Similar case applies to 32 bits.