The image is relating to an example of translating in virtual memory. The address of phys. mem. starts from 0x000 ~ 0x0FC, then moves start 0x100 ~ 0x1FC and so on. Why don't it go like 0x000 ~ 0x0FF, and then 0x100 ~ 0x1FF etc. What are the two lowest bits stand for?
Thank you for your answers. This photo came from MIT open course, and they didn't reveal more details about the address. But I finally figured it out in the later example of the courses.
The two lowest bits can always be zero as the following example:
Supports that we have:
4GB of MM size.
64 lines of cache.
ONLY 1 WORD = 4 bytes PER CACHE LINE.
The address have 32 bits because of 4GB of MM.
The partial address defining the line have 6 bits because of 64 lines of cache.
And because the cache size is 2^6*4B
=> The tag have 24 bits (log2(4GB/2^8B))
=> The lowest bits have 2(32 - 24 - 6) bits.
Because there is only a word per block so that the lowest bits, which act as a data boundary(This is what the course said), are always 0.
Related
I have this question:
1. How many bits are required to address a 4M × 16 main memory if main memory is word-addressable?
And before you say it, yes I have looked this question up and there have been posts on stackoverflow asking about how to answer it but my question is different.
This may sound like a silly question but I don't understand what it means when it says "How many bits are required to address...".
To my understanding and what I have been taught is that (if we're talking about word addressable) each cell would contain 16 bits in the RAM chip and the length would be 4M-1, with 2^22 words. But I don't understand what it is asking when it says 'How many bits are required...':
The answer says 22 bits would be required but I just don't understand. 22 bits for what? All I know is each word is 16 bits and each cell would be numbered from 0 - 4M-1. Can someone clear this up for me please?
Since you have 4 million cells, you need a number that is able to represent each cell. 22 bits is the size of the address to allow representing 2^22 cels (4,194,304 cells)
In computing, a word is the natural unit of data used by a particular processor design. A word is a fixed-sized piece of data handled as a unit by the instruction set or the hardware of the processor.
(https://en.m.wikipedia.org/wiki/Word)
Using this principle imagine a memory with a word that uses 2 bits only, and it is capable of storing 4 words:
XX|YY|WW|ZZ
Each word in this memory is represented by a number that tells to computer it's position.
XX is 0
YY is 1
WW is 2
ZZ is 3
The smallest binary number length that can represent 3 is a 2 bit binary length right? Now apply the same example to a largest memory. Doesn't matters if the word size is 16 bits or 2 bits. Only the length of words matters
Suppose we have a 64 bit processor with 8GB ram with frame size 1KB.
Now main memory size is 2^33 B
So number of frames is 2^33 / 2^10 which is 2^23 frames.
So we need 23 bits to uniquely identify every frame.
So the address split would be 23 | 10 where 10 bits are required to identify each byte in a frame (total 1024 bytes)
As it is word addressable with each word = 8B, will the address split now be 23 | 7 as we have 2^7 words in each frame?
Also can the data bus size be different than word size ?
If suppose data bus size is 128 bits then does it mean that we can address two words and transfer 2 words at a time in a single bus cycle but can only perform 64 bit operations?
Most of the answers are dependent on how the system is designed. Also there is bit more picture to your question.
There is something called available addressable space on a system. In a 32 bit application this would be 2^32 and in a 64 bit application this would be 2^64. This is called virtual memory. And there is physical memory which commonly refereed as RAM. If the application is built as 64 bits, then it is able work as if there is 2^64 memory is available. The underlying hardware may not have 2^64 RAM available, which taken care by the memory management unit. Basically it breaks both virtual memory and physical memory into pages( you have refereed to this as frames) and keeps the most frequently used pages in RAM. Rest are stored in the hard disk.
Now you state, the RAM is 8GB which supports 2^33 addressable locations. When you say the processor is 64 bits, I presume you are talking about a 64 bit system which supports 2^64 addressable locations. Now remember the applications is free to access any of these 2^64 locations. Number of pages available are 2^64/2^10 = 2^54. Now we need to know which virtual page is mapped to which physical page. There is a table called page table which has this information. So we take the first 54 bits of the address and index in to this table which will return the physical page number which will be 2^33/2^10 = 23 bits. We combine this 23 bits to the least 10 bits of the virtual address which gives us the physical address. In a general CPU, once the address is calculated, we don't just go an fetch it. First we check if its available in the cache, all the way down the hierarchy. If its not available a fetch request will be issued. When a cache issues a fetch request to main memory, it fetches an entire cache line (which is usually a few words)
I'm not sure what you mean by the following question.
As it is word addressable with each word = 8B, will the address split now be 23 | 7 as we have 2^7 words in each frame?
Memories are typically designed to be byte addressable. Therefore you'll need all the 33 bits to locate a byte within the page.
Also can the data bus size be different than word size ?
Yes you can design a data bus to have any width, but having it less than a byte would be painful.
If suppose data bus size is 128 bits then does it mean that we can
address two words and transfer 2 words at a time in a single bus cycle
but can only perform 64 bit operations?
Again the question is bit unclear, if the data but is 128 bits wide, and your cache line is wider than 128 bits, it'll take multiple cycles to return data as a response to a cache miss. You wont be doing operations on partial data in the cache (at least to the best of my knowledge), so you'll wait until the entire cache line is returned. And once its there, there is no restriction of what operations you can do on that line.
"The address consists of 16 bits, and the page size is 8KB. The page table thus consists of eight entries that are kept in fast registers."
How do we get the total entries in the page table as 8?
According to the calculation it should be 1.
Total Entries in the Page Table= ((2^16)/(2^3*2^10*2^3))=1.
(The first 2^3 is for 8 in 8KB, the second one is for bytes to bits conversion and 2^10 is for "Kilo" in 8KB.)
Thanks
Memory is byte-addressable hence, you do not need to divide by 2^3 for bytes to bit conversion.
Explaining it further, 16-bits for address means that the processor will generate memory addresses of length 16 bits which will be used to address the byte or half-word or word present starting (or ending - depends on the endianess of the machine) at that 16-bit value.
Now, the page size is the total size of a page in bits which in this case is 2^16 bits. But as memory is byte addressable, hence number of processor addresses in one page will be 2^16/2^3 i.e 2^13 addresses.
Hence number of page table entries are 2^16/2^13 = 8.
I am confused about the definition of word size. I read that the word size of a processor is its data bus width. Like an 8 bit processor has an 8 bit wide data bus. I recently read that the maximum size of the virtual address space is determined by word size i.e. if the word size is n bits the max virtual address space is 2^n -1. But I always thought that maximum virtual address space is determined by address bus width i.e. an n bits wide address bus can address maximum 2^n bytes. So, what is true?
Also, is this related to pointers as an n bit data bus is capable of carrying only an n bit address. So, maximum 2^n bytes can be accessed via pointers.
I'll first say that some of your confusion probably comes from the fact that things were simpler a few decades ago and your understanding of terms is based on these simpler machines.
I am confused about the definition of word size.I read that the word size of a processor is its data bus width. Like an 8 bit processor has an 8 bit wide data bus.
Definitely not. Data bus with is completely unrelated to this. The word size (which has never really been a precise term) of a processor is best loosely defined as the largest natural size for arithmetic which is generally the size of the registers in the machine. This is quite frequently the width of the data path (which is distinctly different from the data bus). The data path is simply the width of the ALUs. The word size is often the same as the pointer size.
I recently read that the maximum size of the virtual address space is determined by word size i.e. if the word size is n bits the max virtual address space is 2^n -1. But i always thought that maximum virtual address space is determined by address bus width i.e. an n bits wide address bus can address maximum 2^n bytes. So, what is true?
No. The size of the virtual address space is simply determined by the number of bits in the virtual page number of the page table (and the TLB). On current amd64 based machines, only 48 bits of the virtual address are useable. The upper 16 are a sign extension of bit 47. On current amd64 machines, the physical address size is 52 bits. These physical address bits are the ones that are sent on the bus. Though even the term bus is really incorrect. Almost all links are point-to-point (DDRx DRAM is an exception) and use a packetized format (header + payload) instead of address wires and data wires.
Also, is this related to pointers as an n bit data bus is capable of carrying only an n bit address. So, maximum 2^n bytes can be accessed via pointers.
Many (almost all even) machines that have a separate address bus, use an address bus that is narrower than the the number of address bits. These bits are simply split up and sent across the bus using multiple clock cycles. DDRx DRAM is another example of this.
the maximum size of the virtual address space is determined by word size
This used to be true, but certain extensions were made to bypass this limitation (namely Physical Address Extension, or PAE) which enables such things as 36 bit memory addresses.
Aside from that, wikipedia defines a word as:
the natural unit of data used by a particular processor design
In almost all cases, this is 32 bits on 32 bit systems and 64 bits on 64 bit systems. You will still frequently find references to 32 bit words on 64 bit systems (partially because amd64 is an extension of intel x86 rather than a revision). Also, as a holdover from the earlier days of modern computing, you will frequently see 32 bit quantities referred to as a DWORD or double word, and 64 bit ones as a QWORD or quad word.
This is something people fight about all the time. I personally use the definition of word size == bus width.
I have a question that I am trying to answer that gives the following situation:
16K Pages
32-bit Virtual Addresses
512MB hard disk, sector-addressable with 16K sectors
8 processes currently running
I am asked:
i) How many process page tables are required?
I think this is a trick question? Surely the answer is just 1.
ii) If a process address register PAR can be up to 32 bits, what is the maxmimum amount of physical memory that can be supported on this machine?
iii) How wide in bits should each entry in a process table be if 64MB physical memory is installed?
Please could anyone give me help/hint with the last two parts as I'm really stuck on them? Thanks!
In case you look on here before the exam later today, it is because it doesn't mean Process address register, it means Page address register!
Try looking at http://cseweb.ucsd.edu/classes/fa03/cse120/Lec08.pdf for some more information including help about segmentation and paging combined
Also, the book in the IC library called Operating Systems concepts with code 005.43SIL says that each process has it's own process page table and can even be segmented itself!
i) I said 8
ii) Well, 32 bits of virtual memory addressing with 14 bits of offset in the page table (2^14 = 16K page length) means there are 18 bits left for the page number. In 32 bits of PAR, this means 14 bits for the page location. If you multiple the amount of page locations by the page size, you get 2^14 * 2^14 = 2^18 which is 256MB of RAM
iii) I got 30 bits. 64MB is 2^26 divided by the page size is 2^26/2^14 = 2^12 which means 12 bits for the page location. From (ii) I calculated that 18 bits are left in the virtual memory address for the page number meaning that it should be 30 bits wide. I also put a comment that since it should be byte-aliged maybe the extra 2 bits can be used so that we know whether it has been written to and whether it is currently being stored on the disk.
Hope this helps!