I have the following property:
property p_0;
$rose(signal_a) |-> $rose(signal_b) ;
endproperty
my problem is, after HW RST, signal_b rises (normal behavior) but the assertion fails, and I want this check to be evaluated only later.
I wanted to work with first_match() with something like below:
p_0_a : assert property ( ! first_match(p_0)) else `uvm_fatal(...)
so that I skip the first match of this property but the compiler generates a syntax error.
Is there a way to skip the evaluation of SVAs after specific number of iterations?
Cascaded implication operators may well help you out, for example something along the lines of:
assert property (reset |-> p_0);
Basically, |=> and |-> are right-associative:
A |=> B |=> C
means
A |=> ( B |=> C )
ie If A happens, check (B |=> C) immediately afterwards. If A does not happen, don't check (B |=> C).
Related
I have scenario of assertion where first a should be high 1 cycle after this b should be high and 1 cycle after that c should be high, after this with 1 cycle delay d should be high
I am confused as to how these assertions should be coded. I have three options please help me which should be followed as correct solution
Option1 : a |=> b |=> c |=> d ;
Option2 : a |=> b ##1 c ##1 d;
Option3 : a ##1 b |=> c ##1 d;
I am getting stuck at these options which one to follow . Please guide me about best solution and as to why
According to me best coding from description would be
a |=> b |=> c ##1 d
Reason : Operator used is Non overlapping Implication operator which tells if antecedent is true then evaluate consequent at next clock tick.Use of this operator is needed as b has to be high only if a is high else not necessary.so,condition of a is implying condition of b.so is the case with c.
But in case of d, statement says delay which means to use ## to specify number of clock cycles delay.
Option 2 is the only correct option (assuming you want this triggered whenever a is high). Implication is true if the antecedent is false or if the consequent is true.
Option1 : a |=> b |=> c |=> d ; -> If !a, this is true, if a ##1 !b, then this is true, if a ##1 b ##1 !c, then this is true. As soon as the antecedent is false, the whole statement is true.
Basically (b |=> c) is true when b is false, which means Option1 says that if a is high AND if b is high on the next cycle AND if c is high on the next cycle then d must be high on the last cycle. That is not what you need.
Although your question is actually requires a then b then c then d. That would require this:
a ##1 b ##1 c ##1 d
Suppose I have an assertion as follows. Now here I want signal A to remain stable for some time after rising up. That is, A should be high until the first occurrence of D == 4 after that it can go low at any time it wants.
Also I dont want to use ##[0:$] in this assertion.
Any help/advice would be very much appreciated. Thank you.
property p_check(A,B,C,D,E);
#(posedge clk) disable iff(!resetn)
$rose(A) ##1 B ##0 (C == 3) ##0 (D != 2) |=> (D == 4)[->1] ##[0:2] (!E throughout A);
endproperty : p_check
You should write this as a separate property.
#(posedge clk) disable iff(!resetn)
$rose(A) |=> $stable(A) until (D==4);
let' say I have two properties;
property p1;
sig_a ##1 sig_b;
endproperty
property p2;
sig_a |=> sig_b;
endproperty
now if i do assertion like this:
a1: assert property (p1);
a2: assert property (p2);
Does a1 and a2 make any difference?
There is difference between system_verilog property and sequence syntax.
property p1 doesn't have triggering condition. In other words , it will always being checked on clocking event. It just mentions sequence of operation to be checked. i.e. sequence in sv assertion. You could assume property p1 in below manner.
property p1;
1'b1 |-> sig_a ##1 sig_b;
endproperty
It will always fail , if sig_a is zero-value.
Now property p2 is having triggering condition which is sig_a == non_zero value. if this condition is true then it will evaluate sig_b value after 1 clocking event.
I have this assertion in order to check clk freq:
assert property clk_freq;
int cnt;
#(posedge fast_clk, clk_1MHz) disable_iff(!enable_check)
($rose(clk_1MHz), cnt=0) |=> (!$rose(clk_1MHz),cnt++) [*0:$] ##1 $rose(clk_1MHz), cnt==fast_clk_freq;
endproperty
fast_clk starts to toggle during (not from beginning) of the simulation after disable_check is asserted.
The problem is that it seems that the assertion ignores the disable_iff
Question: is a $rose(clk_1Mhz) event "registered" even though the assertion is disabled (or am I missing something else ?)
There is no disable_iff keywords, it is disable iff (without the underscore). Properties can have local variables but the local variables cannot be defined inline with assert. Separate the property definition and the assertion instantiation.
The clock sampling doesn't seem to be correct. #(posedge fast_clk, clk_1MHz) mean on rising fast_clk or any change to clk_1MHz. clk_1MHz is the sampled data value, therefore it should not be a clock.
$rose(clk_1MHz), cnt==fast_clk_freq is ilegal syntax, sugest: $rose(clk_1MHz) ##0 cnt==fast_clk_freq
Suggested property definition and the assertion instantiation:
property p_clk_freq;
int cnt;
#(posedge fast_clk) disable iff(!enable_check)
($rose(clk_1MHz), cnt=0) |=> (!$rose(clk_1MHz),cnt++)[*0:$] ##1 $rose(clk_1MHz) ##0 cnt==fast_clk_freq;
endproperty
a_clk_freq : assert property(p_clk_freq);
For more on assertions refer to section 16 of IEEE Std 1800-2012.
property p_no_glitch;
logic data;
#(in[i]) disable iff (!rst_n)
(1, data = !in[i]) |=>
#(posedge clk)
(in[i] == data);
endproperty : p_no_glitch
CHECK_GLITCH : assert property(p_no_glitch) else $error("%m p_no_glitch");
If the module is disabled I get the following message:
Antecedent of the implication never satisfied
is there a flag (or any other way) to switch off the above message ?
the way to go in VCS is -assert quiet+quiet1+nopostproc. Of course it would be better if the SVA 'owner' would add something like disable iff (!rst_n or !en)