Streaming operators usage in the context of serializers in PHY - system-verilog

Question

I have 8:1 serializers and de-serializers based on the data width in our RTL code.As of now we are using for loops for the data path loading and data path reading from the serializers. Can we use streaming operators for this functionality.
Iam new to the streaming operators so exactly i am not getting how to use them in this context.
input [8*DATA_WIDTH-1:0] data_from_user; //WRITE DATA
output [8*DATA_WIDTH-1:0] data_to_user; //READ DATA
output [7:0] data_to_phy_serializer [DATA_WIDTH-1:0];
input [7:0] data_from_phy_deserializer [DATA_WIDTH-1:0];
//WRITE DATA PATH FLOW
always#(posedge clk) begin:WRITE_PATH
for(i = 0 ; i < DATA_WIDTH ; i = i+ 1 )
data_to_phy_serializer[i] = '{
data_from_user[DATA_WIDTH*7 + i],
data_from_user[DATA_WIDTH*6 + i],
data_from_user[DATA_WIDTH*5 + i],
data_from_user[DATA_WIDTH*4 + i],
data_from_user[DATA_WIDTH*3 + i],
data_from_user[DATA_WIDTH*2 + i],
data_from_user[DATA_WIDTH*1 + i],
data_from_user[DATA_WIDTH*0 + i]
} ;
end
//READ DATA PATH FLOW
always#(posedge clk) begin:READ_PATH
for(j= 0 ; j < DATA_WIDTH ; j = j + 1)begin
{
data_to_user[j+DATA_WIDTH*7],
data_to_user[j+DATA_WIDTH*6],
data_to_user[j+DATA_WIDTH*5],
data_to_user[j+DATA_WIDTH*4],
data_to_user[j+DATA_WIDTH*3],
data_to_user[j+DATA_WIDTH*2],
data_to_user[j+DATA_WIDTH*1],
data_to_user[j+DATA_WIDTH*0]
} <= #TCQ data_from_phy_deserializer[j] ;
end
input will be in the form of 8 data words concatenated and i need to the send the data to PHY of each data bit separately by picking up that elements correspondingly from the input data.
this code is working fine but only doubt is can i use streaming operators in this context . Please don't tell the basics of streaming operators, like its for packed to unpacked conversions and viceversa. I need to stream the data for PHY . if i can use streaming operators in this context it will help me so much.
example code for write data path of 4 bit data width to 8:1 serializers
//write data for data width of 4
assign [8*4 -1:0] data = {4'hF,4'hE,4'hD,4'hC,4'hB,4'hA,4'h9,4'h8};
//so now data to each data bit serializer will be
//8:1 data for serializers of
// bit-- 3-- 2-- 1-- 0
// 4'b___1___1___1___1
// 4'b___1___1___1___0
// 4'b___1___1___0___1
// 4'b___1___1___0___0
// 4'b___1___0___1___1
// 4'b___1___0___1___0
// 4'b___1___0___0___1
// 4'b___1___0___0___0
// data for serializer of bit 0 is 8'b10101010
// data for serializer of bit 1 is 8'b11001100
// data for serializer of bit 2 is 8'b11110000
// data for serializer of bit 3 is 8'b11111111
assign [7:0] data_to_phy_serializers [3:0] = '{
8'b11111111,
8'b11110000,
8'b11001100,
8'b10101010
};

Answer 1

Yes you can use it in both cases.I guess this will work:
data_to_phy_serializer = {>>{data_from_user}};
and
data_to_user <= #TCD {>>{data_from_phy_deserializer}};
I have a small experimental example here which you can play with.
module ab;
logic [3:0][1:0]a;
logic [3:0]b[1:0];
logic [3:0][1:0]c;
initial begin
a = 8'hAB;
b = {>>{a}};
c = {>>{b}};
$displayh(a,b[1],b[0],c);
end
endmodule