2D arrays: A net is not a legal lvalue in this context [duplicate] - system-verilog

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Compilation error: A net is not a legal lvalue in this context
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I am looking to create a FIFO using a 2D array (P_MDIM is the width of each vector, P_NDIM is the depth of the array/memory to store these vectors).
I am having trouble with the above error message on many spots in my code (assigning to out, full, and empty).
I don't know why it occurs. I thought my array ("memory") would be a 2D array of reg (not nets). Below is my full code:
module fifo( signal, enqueue, dequeue, clk, out, full, empty );
//depth of the memory
parameter P_NDIM = 16;
//width of each memory cell(in bits)
parameter P_MDIM = 16;
input [P_MDIM - 1:0] signal;
input enqueue;
input dequeue;
input clk;
output [P_MDIM - 1:0] out;
output full;
output empty;
logic [P_MDIM - 1:0] [P_NDIM - 1:0] memory = 0;
integer enqueue_pos = 0;
integer i = 0;
always #(posedge clk) begin
//enqueue data
if(enqueue) begin
//checking if memory is full
if(enqueue_pos == P_NDIM - 1) begin
$display("data not entered, memory full");
end
//add signal into memory
else begin
memory[enqueue_pos][P_MDIM-1:0] = signal;
enqueue_pos <= enqueue_pos + 1;
end//else
end//if enqueue
//dequeue data
if(dequeue) begin
//checking if memory is empty
if(enqueue_pos == 0) begin
$display("no data to dequeue, memory empty");
out[P_MDIM-1:0] = 0;
end
//output signal from memory, shift memory
else begin
out = memory[0][P_MDIM - 1:0];
enqueue_pos <= enqueue_pos - 1;
for(i = 0; i <= P_NDIM - 2; i = i + 1) begin
memory[i][P_MDIM-1:0] = memory[i + 1][P_NDIM-1:0];
end//for
end//else
end//if dequeue
//check full and empty
full = (enqueue_pos == P_NDIM-1 ? 1'b0 : 1'b1);
empty = (enqueue_pos == 0 ? 1'b0 : 1'b1);
end//always
endmodule

Answer 1

You declared out as a net type, but then you assigned to it inside a procedural always block. Signals assigned in a procedural block should be declared as logic:
Change:
output [P_MDIM - 1:0] out;
output full;
output empty;
to:
output logic [P_MDIM - 1:0] out;
output logic full;
output logic empty;
Unrelated to the error, in your always block, you are using a mixture of blocking (=) and nonblocking (<=) assignments. They should all be nonblocking.