Why RISCV choose "push and pop" RAS for coroutines? - cpu-architecture

Question

In riscv-spec-2.2, it provide the following truth table for Return Address Stack (RAS) behavior:
rd rs1 rs1=rd RAS action
!link !link - none
!link link - pop
link !link - push
link link 0 push and pop
link link 1 push
I'm confused about the "push and pop" case, where riscv-spec-2.2 says it's used to support coroutines:
When two different link registers (x1 and x5) are given as rs1 and rd, then the RAS is both pushed and popped to support coroutines"
I also found there is a discussion about the RAS truth table in riscv mailing list, but it didn't explain why "push and pop" for RAS could help coroutines (but it mentioned that Alpha also have this kind of hint for coroutines):
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/uZUTszCtgAA/f3jDhbjEAAAJ
In my understanding, a "push and pop" of RAS will replace the top entry of RAS. Therefore, when the software returning from coroutine, there will be a miss-predict since the correct return address (at RAS top entry in the beginning) was replaced. It seems doesn't have any benefit to perform "push and pop" compare to a simple "push".
Why RISCV choose to "push and pop" RAS for coroutines ?