SystemVerilog compile error when declaring interface for a module (undeclared identifier [12.5(IEEE)]) - interface

Question

I am learning how to use interfaces to wrap around a DUT (top-level module entity) in SystemVerilog. So, for this purpose, I came up with a basic example where the DUT is a simple synchronous RAM.
However, while I try to compile my code, I receive an error for every signal declared in the interface and used in the module ("undeclared identifier [12.5(IEEE)]"). I hope to get the precious help from this community to understand my error. I kept the code short and hopefully readable. Thank you in advance!
I tried removing the parameters and transform them into fixed numbers as well as using the define directive to make them global but did not help. The error, in fact, shows up also with signals that are not parametrized (such as oe signal).
// ********** Define the INTERFACE TO MODULE RAM: **********
interface clocked_bus
#(
// ---------- Parameters definition: ----------
parameter MEM_WIDTH=16, // word size of the memory
parameter ADDR_WIDTH=8 // => [2^ADDR_WIDTH locations]
)
(
// ---------- I/Os declaration: ----------
input clk
);
// ---------- Ports declaration: ----------
logic wr_rd_n_en, oe;
logic [MEM_WIDTH-1:0] data_out;
logic [2**ADDR_WIDTH-1:0] addr;
logic [MEM_WIDTH-1:0] data_in;
endinterface
// ********** Define the MODULE RAM: **********
module RAM(input clk, clocked_bus cb);
// ---------- CREATION OF MEM MATRIX: ----------
logic [MEM_WIDTH-1:0] mem [2**ADDR_WIDTH-1:0];
// ---------- BEHAVIORAL ARCHITECTURE DEFINITION: ----------
always_ff#(posedge clk)
begin
if (wr_rd_n_en == 0)
if (oe ==1)
data_out <= mem[addr];
else
mem[addr] <= data_in;
end
endmodule
// ********** Define the MODULE RAM: **********
module top;
// Define the clock as 'free running process':
logic clk = 0;
always #10 clk = !clk;
// Instantiate the Interface:
clocked_bus #(.MEM_WIDTH(16), .ADDR_WIDTH(8)) cb(clk);
// Instantiate the DUT:
RAM mem1(clk, cb);
endmodule
I expect to compile however I get the following error:
interface worklib.clocked_bus:sv
errors: 0, warnings: 0
logic [MEM_WIDTH-1:0] mem [2**ADDR_WIDTH-1:0];
|
xmvlog: *E,UNDIDN (lab.sv,31|43): 'ADDR_WIDTH': undeclared identifier [12.5(IEEE)].
logic [MEM_WIDTH-1:0] mem [2**ADDR_WIDTH-1:0];
|
xmvlog: *E,UNDIDN (lab.sv,31|19): 'MEM_WIDTH': undeclared identifier [12.5(IEEE)].
if (wr_rd_n_en == 0)
|
xmvlog: *E,UNDIDN (lab.sv,36|21): 'wr_rd_n_en': undeclared identifier [12.5(IEEE)].
if (oe ==1)
|
xmvlog: *E,UNDIDN (lab.sv,37|17): 'oe': undeclared identifier [12.5(IEEE)].
data_out <= mem[addr];
|
xmvlog: *E,UNDIDN (lab.sv,38|23): 'data_out': undeclared identifier [12.5(IEEE)].
data_out <= mem[addr];
|
xmvlog: *E,UNDIDN (lab.sv,38|35): 'addr': undeclared identifier [12.5(IEEE)].
mem[addr] <= data_in;
|
xmvlog: *E,UNDIDN (lab.sv,40|19): 'addr': undeclared identifier [12.5(IEEE)].
mem[addr] <= data_in;
|
xmvlog: *E,UNDIDN (lab.sv,40|31): 'data_in': undeclared identifier [12.5(IEEE)].
module worklib.RAM:sv
errors: 8, warnings: 0
module worklib.top:sv
errors: 0, warnings: 0

Answer 1

When you access variables and parameters inside an interface, you should use the interface name to denote them. An interface provides a namespace capability by encapsulating those. Your code for RAM should look like the following:
module RAM(input clk, clocked_bus cb);
// ---------- CREATION OF MEM MATRIX: ----------
logic [cb.MEM_WIDTH-1:0] mem [2**cb.ADDR_WIDTH-1:0];
// ---------- BEHAVIORAL ARCHITECTURE DEFINITION: ----------
always_ff#(posedge clk)
begin
if (cb.wr_rd_n_en == 0)
if (cb.oe ==1)
cb.data_out <= mem[cb.addr];
else
mem[cb.addr] <= cb.data_in;
end
endmodule