Instead of using
module ... ( .. ) ;
#15
endmodule
I want use
module ... ( ... ) ;
// GateDelay is a const, like in c language const int GateDelay = 15 ;
# GateDelay
endmodule
Or same thing
module ... ( ... ) ;
// assume Wordsize is defined at " define Wordsize 15 "
reg [ Wordsize -1 : 0 ] mem ;
endmodule
Can I do that wish in verilog ?
You've a few options :
Macros with `defines
parameters
localparams
Here's a small example with them all.
`define CONSTANT_MACRO 1 /* important: no ';' here */
module mymodule
#( parameter WIDTH = 5 )
(
input wire [WIDTH-1:0] in_a,
output wire [WIDTH-1:0] out_a
);
localparam CONSTANT_LOCAL = 2;
assign out_a = in_a + `CONSTANT_MACRO - CONSTANT_LOCAL;
endmodule
For the cases you listed, I would recommend parameters.
Like the C compiler directive, `define is global for the compilation. If your code is ever going to be used with code you don't control you will need to be careful here.
Parameters are always local to the module scope so identically named parameters in different design elements will not conflict with each other. They also have the advantage that they can be overridden on a per-instance basis.
module #(parameter DATA_WIDTH = 1) busSlave(
input [DATA_WIDTH-1:0] bus_data,
input bus_wr,
...
);
endmodule
module top;
//DATA_WIDTH is 32 in this instance
busSlave #(.DATA_WIDTH(32)) slave32(
.bus_data(data_0),
.bus_wr(wr_0),
...
);
//DATA_WIDTH is 64 in this instance
busSlave #(.DATA_WIDTH(64)) slave64(
.bus_data(data_1),
.bus_wr(wr_1),
...
);
endmodule
Related
Is it possible to pass around a mailbox types in SystemVerilog using normal module IO? Most of the book examples of mailbox only show them being used inside of SystemVerilog classes. For example, could I do the follow? Is it legal?
module driver(
output mailbox mb
);
mailbox mbx = new(2);
initial begin
for (int i=0; i < 5; i++) begin
#1 mbx.put(i);
$display ("[%0t] Put #%0d, size=%0d",
$time, i, mbx.num());
end
end
endmodule
module sink(
input mailbox mb
);
initial begin
forever begin
int idx;
#2 mbx.get (idx);
$display ("[%0t] Got item #%0d, size=%0d",
$time, idx, mbx.num());
end
end
endmodule
module top;
mailbox mbx;
source(mbx);
sink(mbx);
endmodule
Yes, but your code has many errors. You were mixing up mb and mbx, and your module top was incorrect. Also, I strongly recommend using a parameterized mailbox to make is strongly typed. You'll thank me later when using many mailboxes. The following works for me
typedef mailbox#(int) i_mailbox;
module source(
output i_mailbox mbx
);
initial begin
mbx = new(2);
for (int i=0; i < 5; i++) begin
#1 mbx.put(i);
$display ("[%0t] Put #%0d, size=%0d",
$time, i, mbx.num());
end
#100 $finish;
end
endmodule
module sink(
input i_mailbox mbx
);
initial begin
forever begin
int idx;
#2 mbx.get (idx);
$display ("[%0t] Got item #%0d, size=%0d",
$time, idx, mbx.num());
end
end
endmodule
module top;
i_mailbox mbx;
source so(mbx);
sink si(mbx);
endmodule
I´m new to systemverilog and trying to build a systemverilog testbench.
I have a DUT that should be connected to one of two external modules via a multiplexer. I want to switch the connection during simulation and I want to use systemverilog interfaces for the connection between the DUT and the multiplexer as well as the connection between multiplexer and the two external modules. The signals in the interface are bidirectional.
I am facing trouble writing the multiplexer. I´m getting an error for the current implementation that the LHS of the expression can´t be a wire. If I change the type in the interface to logic, I get an error that this is not possible with bidirectional signals.
I tried to google, but I didn´t find any tutorials on connecting interface to interface. Is this not possible? Or is there a better way of doing what I´m trying to do?
So far I have the following:
interface flash_connect_interface;
wire interface_f_cle;
wire interface_f_ale;
endinterface: flash_connect_interface
module flash_connect_testbench_top;
[...]
// Interfaces
flash_connect_interface flash_connect_interface_i0();
flash_connect_interface flash_connect_interface_i1();
flash_connect_interface flash_connect_interface_i2();
// Connecting DUT to interface
flash_connect flash_connect_i0(
.flash_connect_interface_i(flash_connect_interface_i0),
);
// Multiplexer
flash_connect_mux mux1(
.flash_connect_interface_i_0(flash_connect_interface_i0),
.flash_connect_interface_i_1(flash_connect_interface_i1),
.flash_connect_interface_i_2(flash_connect_interface_i2),
.select(sel)
);
nand_model nand_model0 (
.Cle (flash_connect_interface_i1.interface_f_cle),
.Ale (flash_connect_interface_i1.interface_f_ale),
);
nand_model nand_model1 (
.Cle (flash_connect_interface_i2.interface_f_cle),
.Ale (flash_connect_interface_i2.interface_f_ale),
);
[...]
endmodule // end testbench_top
module flash_connect_mux(
flash_connect_interface flash_connect_interface_i_0,
flash_connect_interface flash_connect_interface_i_1,
flash_connect_interface flash_connect_interface_i_2,
input select
);
always_comb begin
// *** Here is the problem ***
if (select == 1'b0) flash_connect_interface_i_1 = flash_connect_interface_i_0;
else flash_connect_interface_i_2 = flash_connect_interface_i_0;
end
endmodule
The interfaces in this case is just bundle of wires . There seems nothing apparently wrong with your code. But if you are trying to assign interface directly to each other based on the select signal it will not work. You will need to assign all the wires individually based on the select signal. There is nothing special to mux interfaces.
The code below does the muxing.
interface flash_connect_interface;
wire interface_f_cle;
wire interface_f_ale;
endinterface: flash_connect_interface
module nand_model ( inout Cle , inout Ale ) ; // Sample nand model
reg r = 1;
assign Cle = r?1:1'bz;
assign Ale = r?1:1'bz;
endmodule
module flash_connect_mux ( flash_connect_interface flash_connect_interface_i_0 , flash_connect_interface flash_connect_interface_i_1 , flash_connect_interface
flash_connect_interface_i_2 ,input [3:0] select ) ;
// Interconnect interface assignment
assign flash_connect_interface_i_0.interface_f_cle = (select== 0) ? flash_connect_interface_i_1.interface_f_cle : flash_connect_interface_i_2.interface_f_cle;
assign flash_connect_interface_i_0.interface_f_ale = (select== 0) ? flash_connect_interface_i_1.interface_f_ale : flash_connect_interface_i_2.interface_f_ale;
endmodule
module flash_connect ( flash_connect_interface flash_connect_interface_i ) ;
//check flash_connect_interface_i.interface_f_cle ;
//check flash_connect_interface_i.interface_f_ale ;
endmodule
module flash_connect_testbench_top;
reg [3:0] select ;
// Interfaces
flash_connect_interface flash_connect_interface_i0();
flash_connect_interface flash_connect_interface_i1();
flash_connect_interface flash_connect_interface_i2();
// Connecting DUT to interface
flash_connect flash_connect_i0(
.flash_connect_interface_i(flash_connect_interface_i0)
);
// Multiplexer
flash_connect_mux mux1(
.flash_connect_interface_i_0(flash_connect_interface_i0),
.flash_connect_interface_i_1(flash_connect_interface_i1),
.flash_connect_interface_i_2(flash_connect_interface_i2),
.select(select)
);
nand_model nand_model0 (
.Cle (flash_connect_interface_i1.interface_f_cle),
.Ale (flash_connect_interface_i1.interface_f_ale)
);
nand_model nand_model1 (
.Cle (flash_connect_interface_i2.interface_f_cle),
.Ale (flash_connect_interface_i2.interface_f_ale)
);
endmodule // end testbench_top
Link to interface tutorial -
https://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/
Can s_clk be passed as argument to xyz task in below code?
module test(input logic m_clk, output [1:0] logic s_clk);
...
xyz (m_clk,s_clk);//assuming m_clks and s_clks are generated from top
...
task automatic xyz (ref logic clk1, ref [1:0] logic clk2);
...
endtask
endmodule
I have read your problem, first of all you have typo mistake
module test(input logic m_clk, output [1:0] logic s_clk);
task automatic xyz (ref logic clk1, ref [1:0] logic clk2);
instead of this you have to write
module test(input logic m_clk, output logic [1:0] s_clk);
task automatic xyz (ref logic clk1, ref logic [1:0] clk2);
For better understanding I have also share one demo code for packed arrays can be passed by reference to the task in systemverilog.
Here is code :
program main();
bit [31:0] a = 25;
initial
begin
#10 a = 7;
#10 a = 20;
#10 a = 3;
#10 $finish;
end
task pass_by_val(int i);
$monitor("===============================================%d",i);
forever
#a $display("pass_by_val: I is %0d",i);
endtask
task pass_by_ref(ref bit [31:0]i);
forever
begin
#a $display("pass_by_ref: I is %0d",i[0]);
$display("This is pass_by value a ====== %d \n a[0] ====== %0d ",a,a[0]);
end
endtask
initial
begin
pass_by_val(a);
end
initial
pass_by_ref(a);
endprogram
By running this example you can observe that packed arrays can be passed by reference to the task in systemverilog and its value is also reflected to it.
pass_by_val task will register the value of the variables
only once at the time when task is called. Subsequently when the variable changes its value, pass_by_val task cannot see the newer values. On the other hand, 'ref' variables in a task are registered whenever its value changes. As a result, when the variable 'a' value changes, the pass_by_ref task can register and display the value correctly.
I simulated Ashutosh Rawal's code and the output display is given below:
=============================================== 25
pass_by_val: I is 25
pass_by_ref: I is 1
This is pass_by value a ====== 7
a[0] ====== 1
pass_by_val: I is 25
pass_by_ref: I is 0
This is pass_by value a ====== 20
a[0] ====== 0
pass_by_val: I is 25
pass_by_ref: I is 1
This is pass_by value a ====== 3
a[0] ====== 1
$finish called from file "testbench.sv", line 13.
$finish at simulation time 40
V C S S i m u l a t i o n R e p o r t
I am trying to make a block for an 8-bit multiplier, and the testbench is giving me a result that basically says that I don't know what I'm doing with my wires and regs. To make this easier to answer, I'm going to display my code, and then the parts that I think are important:
module multiplier_result(
input ADD_cmd,
input LOAD_cmd,
input SHIFT_cmd,
input reset,
input [7:0] B_in,
input [7:0] Add_out,
input cout,
output wire [7:0] RB,
output wire [15:0] RC,
output wire [8:0] temp_reg,
output wire LSB
);
wire [8:0] from_mux;
reg[16:0] balreg;
reg tempadd;
//assign the outputs. all combinational
assign RB = balreg[15:8];
assign RC = balreg[15:0];
assign LSB = balreg[0];
assign temp_reg = balreg[16:8];
mux_9 mux(
.sel(~ADD_cmd),
.Add_out(Add_out),
.cout(cout),
.mux_out(from_mux),
.temp_reg(temp_reg)
);
always # (*) begin
if(reset) begin
balreg[16:0] = 17'd0;
tempadd = 1'b0;
end
else
begin
if(LOAD_cmd)
begin
balreg[16:8] = 9'b000000000;
balreg[7:0] = B_in;
end
if(SHIFT_cmd)
begin
balreg[16:8] = from_mux;
balreg = balreg >> 1;
end
end
end
endmodule
Now, here is what's troubling me:
Here I'm assigning wires to different bits of the balreg register (in black). What is going on in my head (please excuse my paint skills):
But for some reason, LSB gets what it's supposed to, while RB and RC get high impedance. Here is the simulate result, followed by the code I used (just a simple test case)
module multiplier_result_tb(
);
reg ADD_cmd;
reg LOAD_cmd;
reg SHIFT_cmd;
reg reset;
reg [7:0] B_in;
reg [8:0] Add_out;
wire [7:0] RB;
wire [15:0] RC;
wire [8:0] temp_reg; //size 9
wire LSB;
multiplier_result dut(ADD_cmd,LOAD_cmd,SHIFT_cmd,reset,B_in,Add_out,RB,RC,temp_reg,LSB);
initial begin
LOAD_cmd = 0;
#10;
LOAD_cmd = 1;
reset = 0;
B_in = 8'b00001010;
Add_out = 9'd0;
ADD_cmd = 0;
SHIFT_cmd = 0;
end
endmodule
I'm not following these results at all. The balreg register is all set up, so the RB and RC wires MUST be defined, but according to the simulation, they are high impedance.
The only conclusion that I get at, is that I really don't know what's going on with the types (the model I had in my had worked for me so far).
Any help, ideas, tips are much appreciated.
You only connected 10 of the 11 ports of the dut. Didn't you get a warning? You are making connections by position, not by name. You connected RB to input cout. You need to drive cout in your testbench.
Another way to make connections is by name. This is more verbose, but it can make your code clearer:
multiplier_result dut (
// Inputs:
.ADD_cmd (ADD_cmd),
.Add_out (Add_out),
.B_in (B_in),
.LOAD_cmd (LOAD_cmd),
.SHIFT_cmd (SHIFT_cmd),
.cout (cout),
.reset (reset),
// Outputs:
.LSB (LSB),
.RB (RB),
.RC (RC),
.temp_reg (temp_reg)
);
I am trying to make a module (a DSP in my case) with a standardized memory interface in SystemVerilog, and would like the variables in the module to size automatically based on the bus widths in the attached interface. My rationale: this makes the code more portable by allowing it to auto-size to any connected interface, instead of requiring an HDL coder to pass in parameters that tell the module the widths of all the interface busses that will connect to it (not that this would be terrible, it just seems cleaner without the parameters).
I can't seem to get this to work, however. Here's an example that illustrates the problem; the following synthesizes in Quartus II 12.1:
// Top level module with some 15-bit ports
module top ( input [14:0] data_in,
output [14:0] data_out1, data_out2,
data_out3, data_out4 );
test_interface my_interface(); // Initialize the interface
test_module my_module(.*); // Initialize & connect module
endmodule
// Define a simple interface:
interface test_interface ();
logic [8:0] my_port;
endinterface
// Define the module:
module test_module ( input [14:0] data_in,
test_interface my_interface,
output [14:0] data_out1, data_out2,
data_out3, data_out4 );
localparam width1 = $size(data_in); // should be 15
localparam width2 = $size(my_interface.my_port); // should be 9
logic [width1-1:0] auto_sized1; // gets correct size (14:0)
logic [width2-1:0] auto_sized2; // **PROBLEM**: gets size of 0:0!
always_comb begin
auto_sized1 = 5; // ok
auto_sized2 = 5; // problem; value now truncated to 1
data_out1 = data_in + width1; // Yields data_in + 15 (ok)
data_out2 = data_in + width2; // Yields data_in + 9 (ok...!)
data_out3 = data_in + auto_sized1; // Yields data_in + 5 (ok)
data_out4 = data_in + auto_sized2; // Yields data_in + 1 (problem)
end
endmodule
Note that width2 does eventually get the correct value (9) - just too late for it to correctly set the width of auto_sized2. I initially thought that $size was simply evaluated after all variables had been assigned their widths, but this doesn't seem to be the case either since $size(data_in) works just fine for setting the width of auto_sized1.
Any thoughts? Again, it's not critical to the project's success, I'm mostly curious at this point!
Thanks -
Looks like a compiler bug. I'd probably use a parameter in the interface definition.
module top ( input [14:0] data_in,
output [14:0] data_out1, data_out2,
data_out3, data_out4 );
test_interface #(.port_size(8)) my_interface(); // Initialize the interface
test_module my_module(.*); // Initialize & connect module
endmodule
interface test_interface ();
parameter port_size = 1;
logic [port_size-1:0] my_port;
endinterface
module test_module ( input [14:0] data_in,
test_interface my_interface,
output [14:0] data_out1, data_out2,
data_out3, data_out4 );
localparam width1 = $size(data_in);
localparam width2 = my_interface.port_size;
endmodule