I am trying to make a module (a DSP in my case) with a standardized memory interface in SystemVerilog, and would like the variables in the module to size automatically based on the bus widths in the attached interface. My rationale: this makes the code more portable by allowing it to auto-size to any connected interface, instead of requiring an HDL coder to pass in parameters that tell the module the widths of all the interface busses that will connect to it (not that this would be terrible, it just seems cleaner without the parameters).
I can't seem to get this to work, however. Here's an example that illustrates the problem; the following synthesizes in Quartus II 12.1:
// Top level module with some 15-bit ports
module top ( input [14:0] data_in,
output [14:0] data_out1, data_out2,
data_out3, data_out4 );
test_interface my_interface(); // Initialize the interface
test_module my_module(.*); // Initialize & connect module
endmodule
// Define a simple interface:
interface test_interface ();
logic [8:0] my_port;
endinterface
// Define the module:
module test_module ( input [14:0] data_in,
test_interface my_interface,
output [14:0] data_out1, data_out2,
data_out3, data_out4 );
localparam width1 = $size(data_in); // should be 15
localparam width2 = $size(my_interface.my_port); // should be 9
logic [width1-1:0] auto_sized1; // gets correct size (14:0)
logic [width2-1:0] auto_sized2; // **PROBLEM**: gets size of 0:0!
always_comb begin
auto_sized1 = 5; // ok
auto_sized2 = 5; // problem; value now truncated to 1
data_out1 = data_in + width1; // Yields data_in + 15 (ok)
data_out2 = data_in + width2; // Yields data_in + 9 (ok...!)
data_out3 = data_in + auto_sized1; // Yields data_in + 5 (ok)
data_out4 = data_in + auto_sized2; // Yields data_in + 1 (problem)
end
endmodule
Note that width2 does eventually get the correct value (9) - just too late for it to correctly set the width of auto_sized2. I initially thought that $size was simply evaluated after all variables had been assigned their widths, but this doesn't seem to be the case either since $size(data_in) works just fine for setting the width of auto_sized1.
Any thoughts? Again, it's not critical to the project's success, I'm mostly curious at this point!
Thanks -
Looks like a compiler bug. I'd probably use a parameter in the interface definition.
module top ( input [14:0] data_in,
output [14:0] data_out1, data_out2,
data_out3, data_out4 );
test_interface #(.port_size(8)) my_interface(); // Initialize the interface
test_module my_module(.*); // Initialize & connect module
endmodule
interface test_interface ();
parameter port_size = 1;
logic [port_size-1:0] my_port;
endinterface
module test_module ( input [14:0] data_in,
test_interface my_interface,
output [14:0] data_out1, data_out2,
data_out3, data_out4 );
localparam width1 = $size(data_in);
localparam width2 = my_interface.port_size;
endmodule
Related
I'm trying to implement an interface with modports. I have 2 modules inside a testbench.
module test;
test_intf intf();
clk_reset u_clk_reset (
intf.CLK_RESET
);
mem u_mem(
intf.MEM
);
....
endmodule
This is the interface:
interface test_intf;
logic reset_n;
logic aclk;
logic bclk;
logic areset_n;
logic wr_in;
logic rd_en;
logic [ 9:0] wr_addr;
logic [23:0] wr_data;
logic [ 9:0] rd_addr;
logic [23:0] rd_data;
modport CLK_RESET (output aclk, bclk, areset_n);
modport MEM (output rd_data, input clk, reset_n, wr_in, rd_en, wr_addr, wr_data, rd_addr);
endinterface
This is the clk_reset module:
module clk_reset(
test_intf intf
);
always #(5) intf.aclk = ~intf.aclk;
initial begin
intf.aclk = 0;
end
initial begin
intf.areset_n = 1;
#2000 intf.areset_n = 0;
#2000 intf.areset_n = 1;
end
This is the mem module:
module mem
(
test_intf intf
);
always #(posedge intf.clk or negedge intf.reset_n)
begin
//end
end
I checked that the clk_reset interface ports are working (all outputs).
But, the problem is that the output clock signals from clk_reset can't reach the mem module by interface. So, intf.clk signal is 'x' in the mem module.
How do I pass some interface's signals into another interface (module)?
Your simulator should have given you a compile error. The interface is missing the declaration of the clk signal. Add it like this:
logic clk;
Since you want to use clk inside mem, you need to add clk to the CLK_RESET modport list:
modport CLK_RESET (output aclk, bclk, clk, areset_n);
Finally, you need to generate the clk signal so that it is not X. Here are the required changes:
interface test_intf;
logic reset_n;
logic aclk;
logic bclk;
logic clk;
logic areset_n;
logic wr_in;
logic rd_en;
logic [ 9:0] wr_addr;
logic [23:0] wr_data;
logic [ 9:0] rd_addr;
logic [23:0] rd_data;
modport CLK_RESET (output aclk, bclk, clk, areset_n);
modport MEM (output rd_data, input clk, reset_n, wr_in, rd_en, wr_addr, wr_data, rd_addr);
endinterface
module clk_reset(
test_intf intf
);
always #(5) intf.aclk = ~intf.aclk;
initial begin
intf.aclk = 0;
end
always #(5) intf.clk = ~intf.clk;
initial begin
intf.clk = 0;
end
initial begin
intf.areset_n = 1;
#2000 intf.areset_n = 0;
#2000 intf.areset_n = 1;
end
endmodule
My codes for Alu and Mux:
module alu(input logic [31:0]srca, srcb,
input logic [2:0] alucontrol,
output logic zero,
output logic [31:0]aluout);
logic [31:0] addr, subr, sltr, Andr, Orr;
assign addr = srca + srcb;
assign subr = srca - srcb;
assign sltr = (srca < srcb) ? 1 : 0;
assign Andr = srca & srcb;
assign Orr = srca | srcb;
always_comb
begin
case(alucontrol)
3'b010: aluout = addr;
3'b110: aluout = subr;
3'b111: aluout = sltr;
3'b000: aluout = Andr;
3'b001: aluout = Orr;
default: aluout = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
endcase
zero = (subr == 0) ? 1 : 0;
end
endmodule
module mux2#(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
always_comb
begin
y = s?d1 : d0;
end
endmodule
and their instantiation under the same top module:
alu alu(srca, srcb, alucontrol, aluout, zero);
mux2 #(32) resmux(aluout, readdata, memtoreg, result);
When I try to connect my 2-1Mux resmux with my alu, the aluout doesn't get connected to resmux
aluout gets suspended
I could solve this by exchanging the order of aluout and zero, but could anybody explain why this happens and how to avoid? Thanks a lot!
There are a number of mechanisms for connecting ports in SystemVerilog. The mechanism you are using is positional. That means each signal connection has to go in the prescribed order that they appear in the module declaration of alu. The way your code is written, the signal zero in module top is connected to last port aluout declared in module alu.
SystemVerilog also has a by_name syntax .portname(signal). You can list all your port connections in any order that way.
alu alu(.srca(srca), .srcb(srcb), .alucontrol(alucontrol), .alu(aluout), .zero(zero));
When the signal name you are connecting matches the declared port name, you can just use .portname.
alu alu(.alucontrol, .aluout, .zero, .srca, .srcb);
And finally, if all the port names match the signal names, you can use a wildcard, .* as well as list exceptions explicitly
alu alu(.*, .zero(my_zero));
I have an system verilog interface
interface add_sub_if(
input bit clk,
input [7:0] a,
input [7:0] b,
input doAdd,
input [8:0] result
);
clocking dut_cb #(posedge clk);
output a;
output b;
output doAdd;
input result;
endclocking // cb
modport dut(clocking dut_cb);
endinterface: add_sub_if
And i have a SV module which uses this interface
module dummy(add_sub_if.dut _if);
....
endmodule: dummy
What is the ideal way to hook up this in my TB?
If i instantiate the interface, i need to create wires.
If i use bind then also i need to do a port mapping of the individual signals, that beats the convenience of having an interface.
Another add on question is, how to assign one such interface to another interface?
Thanks in advance,
Rajdeep
You can find a simple example of an interface definition and usage in the IEEE Std 1800-2012 Section 3.5 (Interfaces). It shows how to define the interface and hook it up to the design (the way you have already done it). It also shows how the interface can be instantiated (and connected) inside a top level module/wrapper (I copied the code below directly from the spec for your convenience):
interface simple_bus(input logic clk); // Define the interface
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
endinterface: simple_bus
module memMod(simple_bus a); // simple_bus interface port
logic avail;
// When memMod is instantiated in module top, a.req is the req
// signal in the sb_intf instance of the 'simple_bus' interface
always #(posedge clk) a.gnt <= a.req & avail;
endmodule
module cpuMod(simple_bus b); // simple_bus interface port
...
endmodule
module top;
logic clk = 0;
simple_bus sb_intf(.clk(clk)); // Instantiate the interface
memMod mem(.a(sb_intf)); // Connect interface to module instance
cpuMod cpu(.b(sb_intf)); // Connect interface to module instance
endmodule
Once you have the interface hooked up, then you can have drive/sample all the signals from a testcase program (just remember that you have to pass the interface to it). In this case, it would be be something like:
program testcase(simple_bus tb_if);
initial begin
tb_if.mode <= 0;
repeat(3) #20 tb_if.req <= 1'b1;
[...]
$finish;
end
endprogram
For a real-world example, you can check the source code of a UVM testbench that is available on my GitHub page. The interface hook-up is done in the xge_test_top.sv file.
Here is fsm dut with testbench.
This fsm dut performs state transition 1 - 0 - 1 - 0 in sequence.
Test bench verifies dut is properly working or not.
verilog module code(dut) :
module melay_fsm(o,clk,rst,i);
output o;
input i,clk,rst;
reg o;
reg [1:0]state;
// [1:0]state;
always#(posedge clk,posedge rst)
begin
if(rst)
begin
state <=2'b00;
end
else
begin
case(state)
2'b00:
begin
if(i)
state<=2'b01;
else
state<=2'b00;
end
2'b01:
begin
if(!i)
state<=2'b10;
else
state<=2'b01;
end
2'b10:
begin
if(i)
state<=2'b11;
else
state<=2'b00;
end
2'b11:
begin
if(!i)
state<=2'b00;
else
state<=2'b01;
end
endcase
end
end
always#(posedge clk,negedge rst)
begin
if(rst)
o<=1'b0;
else if(state==2'b11 && i==0)
o<=1'b1;
else
o<=1'b0;
end
endmodule
System verilog module code(testbench) :
interface melay_intf(input bit clk);
logic o,rst,i;
wire clk;
clocking c1#(posedge clk);
input o;
output i,rst;
endclocking
modport tes(clocking c1);
endinterface
module top;
bit clk;
always
#1 clk = ~clk;
melay_intf i1(clk);
melay_fsm a1(.o(i1.o),.clk(i1.clk),.rst(i1.rst),.i(i1.i));
melay_tes(i1);
endmodule
program melay_tes(melay_intf i1);
initial
#100 $finish;
initial
begin
i1.rst <= 0;
#4 i1.rst <= 1;
#4 i1.rst <= 0;
i1.i = 1;
#2 i1.i = 0;
#2 i1.i = 1;
#2 i1.i = 0;
#2 i1.i = 1;
#2 i1.i = 0;
repeat(10)
begin
i1.i = 1;
#2 i1.i = $urandom_range(0,1);
end
end
initial
$monitor("output = %d clk = %d rst = %d i = %d",i1.o,i1.clk,i1.rst,i1.i);
initial
begin
$dumpfile("mem.vcd");
$dumpvars();
end
endprogram
Important thing to note down here is connection of signals in top module.
melay_fsm a1(.o(i1.o),.clk(i1.clk),.rst(i1.rst),.i(i1.i));
Please, observe properly how I bind interface with testbench and dut.
Please, observe following things.
I defines interface with all the dut's signals.
I took instance(i1) of interface(melay_intf) in top module.
I took instance (a1) of dut (melay_fsm) in top module.
Now observes melay_fsm a1(.o(i1.o),.clk(i1.clk),.rst(i1.rst),.i(i1.i))
All the dut's signals are connected with interface.
I passed instance of interface(i1) in testbench. melay_tes(i1)
So, testbench can access interface signals and interface signals are connected to dut's signals.
Now, you can access dut's signals in your test bench with help of interface.
I think now you can understand proper flow.
Please ask the question if you have any doubt.
You can bind interface in system verilog module.
Here, I provides sample code with help of that you can understood how to bind interface in system verilog module and with dut.
Here I provides verilog module and system verilog module. Main part of code is interface from which verilog and system verilog module are connected.
verilog module code(dut) :
module dff(qn,d,clk,reset);
output qn;
input d,clk,reset;
reg qn;
always#(posedge clk,negedge reset)
begin
if (!reset)
begin
qn=1'bx;
end
else if (d==0)
begin
qn=0;
end
else if (d==1)
begin
qn=1;
end
end
endmodule
System verilog module code(testbench) :
interface melay_intf(input bit clk);
logic o,clk,rst,i;
clocking c1#(posedge clk);
input o;
output i,rst;
endclocking
endinterface
module top;
bit clk;
always
#1 clk = ~clk;
melay_intf i1(clk);
dff d1(.o(i1.o),.clk(i1.clk),.rst(i1.rst),.i(i1.i));
melay_tes(i1.tes);
endmodule
program melay_tes(melay_intf i1);
initial
#100 $finish;
initial
begin
i1.rst <= 0;
#4 i1.rst <= 1;
#4 i1.rst <= 0;
i1.i = 1;
#2 i1.i = 0;
#2 i1.i = 1;
#2 i1.i = 0;
#2 i1.i = 1;
#2 i1.i = 0;
repeat(10)
begin
i1.i = 1;
#2 i1.i = $urandom_range(0,1);
end
end
initial
$monitor("output = %d clk = %d rst = %d i = %d",i1.o,i1.clk,i1.rst,i1.i);
initial
begin
$dumpfile("mem.vcd");
$dumpvars();
end
endprogram
Here important part is interface and in it I used clocking block for synchronization purpose. Here clocking c1#(posedge clk); so all signals which are mention inside the clocking block which are i,o,rst.All this signal change its value at every posedge of clk signal.
Here dff d1(.o(i1.o),.clk(i1.clk),.rst(i1.rst),.i(i1.i)); Important thing that you find in top module I made connection between verilog signals and system verilog signals.
You can find verilog module name is "dff". I took the instance of dff verilog module and made the connection. Here i1.o,i1.clk,i1.rst,i1.i is system verilog signals which are connected to o,clk,rst,i signals of verilog module of with dot convention.
I am trying to make a block for an 8-bit multiplier, and the testbench is giving me a result that basically says that I don't know what I'm doing with my wires and regs. To make this easier to answer, I'm going to display my code, and then the parts that I think are important:
module multiplier_result(
input ADD_cmd,
input LOAD_cmd,
input SHIFT_cmd,
input reset,
input [7:0] B_in,
input [7:0] Add_out,
input cout,
output wire [7:0] RB,
output wire [15:0] RC,
output wire [8:0] temp_reg,
output wire LSB
);
wire [8:0] from_mux;
reg[16:0] balreg;
reg tempadd;
//assign the outputs. all combinational
assign RB = balreg[15:8];
assign RC = balreg[15:0];
assign LSB = balreg[0];
assign temp_reg = balreg[16:8];
mux_9 mux(
.sel(~ADD_cmd),
.Add_out(Add_out),
.cout(cout),
.mux_out(from_mux),
.temp_reg(temp_reg)
);
always # (*) begin
if(reset) begin
balreg[16:0] = 17'd0;
tempadd = 1'b0;
end
else
begin
if(LOAD_cmd)
begin
balreg[16:8] = 9'b000000000;
balreg[7:0] = B_in;
end
if(SHIFT_cmd)
begin
balreg[16:8] = from_mux;
balreg = balreg >> 1;
end
end
end
endmodule
Now, here is what's troubling me:
Here I'm assigning wires to different bits of the balreg register (in black). What is going on in my head (please excuse my paint skills):
But for some reason, LSB gets what it's supposed to, while RB and RC get high impedance. Here is the simulate result, followed by the code I used (just a simple test case)
module multiplier_result_tb(
);
reg ADD_cmd;
reg LOAD_cmd;
reg SHIFT_cmd;
reg reset;
reg [7:0] B_in;
reg [8:0] Add_out;
wire [7:0] RB;
wire [15:0] RC;
wire [8:0] temp_reg; //size 9
wire LSB;
multiplier_result dut(ADD_cmd,LOAD_cmd,SHIFT_cmd,reset,B_in,Add_out,RB,RC,temp_reg,LSB);
initial begin
LOAD_cmd = 0;
#10;
LOAD_cmd = 1;
reset = 0;
B_in = 8'b00001010;
Add_out = 9'd0;
ADD_cmd = 0;
SHIFT_cmd = 0;
end
endmodule
I'm not following these results at all. The balreg register is all set up, so the RB and RC wires MUST be defined, but according to the simulation, they are high impedance.
The only conclusion that I get at, is that I really don't know what's going on with the types (the model I had in my had worked for me so far).
Any help, ideas, tips are much appreciated.
You only connected 10 of the 11 ports of the dut. Didn't you get a warning? You are making connections by position, not by name. You connected RB to input cout. You need to drive cout in your testbench.
Another way to make connections is by name. This is more verbose, but it can make your code clearer:
multiplier_result dut (
// Inputs:
.ADD_cmd (ADD_cmd),
.Add_out (Add_out),
.B_in (B_in),
.LOAD_cmd (LOAD_cmd),
.SHIFT_cmd (SHIFT_cmd),
.cout (cout),
.reset (reset),
// Outputs:
.LSB (LSB),
.RB (RB),
.RC (RC),
.temp_reg (temp_reg)
);
Instead of using
module ... ( .. ) ;
#15
endmodule
I want use
module ... ( ... ) ;
// GateDelay is a const, like in c language const int GateDelay = 15 ;
# GateDelay
endmodule
Or same thing
module ... ( ... ) ;
// assume Wordsize is defined at " define Wordsize 15 "
reg [ Wordsize -1 : 0 ] mem ;
endmodule
Can I do that wish in verilog ?
You've a few options :
Macros with `defines
parameters
localparams
Here's a small example with them all.
`define CONSTANT_MACRO 1 /* important: no ';' here */
module mymodule
#( parameter WIDTH = 5 )
(
input wire [WIDTH-1:0] in_a,
output wire [WIDTH-1:0] out_a
);
localparam CONSTANT_LOCAL = 2;
assign out_a = in_a + `CONSTANT_MACRO - CONSTANT_LOCAL;
endmodule
For the cases you listed, I would recommend parameters.
Like the C compiler directive, `define is global for the compilation. If your code is ever going to be used with code you don't control you will need to be careful here.
Parameters are always local to the module scope so identically named parameters in different design elements will not conflict with each other. They also have the advantage that they can be overridden on a per-instance basis.
module #(parameter DATA_WIDTH = 1) busSlave(
input [DATA_WIDTH-1:0] bus_data,
input bus_wr,
...
);
endmodule
module top;
//DATA_WIDTH is 32 in this instance
busSlave #(.DATA_WIDTH(32)) slave32(
.bus_data(data_0),
.bus_wr(wr_0),
...
);
//DATA_WIDTH is 64 in this instance
busSlave #(.DATA_WIDTH(64)) slave64(
.bus_data(data_1),
.bus_wr(wr_1),
...
);
endmodule