Beaglebone's SPI1 interface has 2 native CS. I want to add 4 more GPIO CS to SPI1. Total 6 CS.
I added all 6 CS entries to the device tree's cs-gpios as shown below.
cs-gpios = <0>,
<0>,
<&gpio3 19 GPIO_ACTIVE_HIGH>,
<&gpio1 18 GPIO_ACTIVE_HIGH>,
<&gpio1 16 GPIO_ACTIVE_HIGH>,
<&gpio1 17 GPIO_ACTIVE_HIGH>;
While testing I observed that only devices connected to the first 4 CS works well. The transaction with the last 2 devices throws a timeout error (timeout error verified from dmesg).
After looking at am33xx.dtsi and spi-omap2-mcspi.c driver file, it seems like the SPI driver support only 4 CS.
How do I extend the SPI driver to support 6 CS?
Basically, I am trying to interface 6 mcp4921 devices via SPI1.
Using kernel version 4.14.108-ti-r134.
References
Beaglebone's version.sh output here
spi-omap2-mcspi driver
mcp4922 driver
omap2 dtsi
omap4 dtsi
Related
Is the PCIe ECAM exactly the same as the "PCI-Compatible Configuration Registers" only mapped to memory instead of I/O?
It seems to me that PCIe uses the same Configuration Mechanism as conventional PCI: [1]
| 31 | 30 - 24 | 23 - 16 | 15 - 11 | 10 - 8 | 7 - 2 | 1 - 0 |
| Enable | Reserved | Bus Nr | Device Nr | Function Nr | Register Nr | 00 |
But in PCIe you can use the reserved bytes to address more registers of a function.
Is this correct?
In section 7.2.1 [2] the ECAM is defined as:
| 27 - 20 | 19 - 15 | 14 - 12 | 11 - 8 | 7 - 2 | 1 - 0 |
| Bus Nr | Dev Nr | Function Nr | Ext. Register Nr | Register Nr | Byte Enable |
It looks very similar to the conventional configuration.
Just the reserved bits are shifted to the register number which they extend in PCIe.
But I can use them like the old one? Only address them in memory space not IO space?
[1] https://wiki.osdev.o/PCI#Configuration_Space_Access_Mechanism_.231
[2] in PCI Express Base Specification, Rev. 4.0 Version 1.0
You're mixing apples and oranges in your comparison. The first address decoding is provided by a host bridge component on PC-AT architecture systems (*). It's a way of using the Intel processor's I/O address space to interface to the PCI bus configuration space mechanism. It can also be used on a PCIe system, because the PCIe host bridge component provides the same interface to PCIe devices. However, everything below the host bridge is implemented quite differently between PCI and PCIe.
Meanwhile the second decoding scheme you showed can only be used within the memory-mapped block through which PCIe provides access to its extended configuration space. And only after that block has been mapped into the physical address space in a system-dependent way.
So while they have a similar function, no, you cannot use them in the same way. You can:
Access the first 256 bytes of any PCI or PCIe device's configuration space using the first mechanism, but you must use the first addressing scheme, OR
Access the entire extended configuration space of any PCIe device using the second mechanism (including the first 256 bytes), but then you must use the second addressing scheme.
(*) The "I/O space interface to PCI bus configuration via 0xCF8 / 0xCFC" really is part of the Intel / PC-AT architecture. Other system architectures (MIPS for example) don't have separate I/O address spaces, and host bridges designed for them have different mechanisms to generate PCIe configuration space accesses (or they simply use the memory-mapped mechanism directly).
I need to be connect to 2 STM32s over 2 ST-Links at the same time. I found this issue described here.
However, solution doesn't work for me.
ST-Link ID1: 55FF6B067087534923182367
ST-Link ID2: 49FF6C064983574951291787
OpenOCD cfg file:
source [find interface/stlink-v2.cfg]
hla_serial "55FF6B067087534923182367"
source [find target/stm32f4x.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate
I get:
$ openocd.exe -f stm32f4_fmboard.cfg
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 2000 kHz
adapter_nsrst_delay: 100
none separate
srst_only separate srst_nogate srst_open_drain connect_deassert_srst
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : clock speed 1800 kHz
Error: open failed
in procedure 'init'
in procedure 'ocd_bouncer'
I do not know if solved but:
pi#raspberrypi:~/prog/bootloader $ st-info --probe
Found 1 stlink programmers
serial: 363f65064b46323613500643
openocd: "\x36\x3f\x65\x06\x4b\x46\x32\x36\x13\x50\x06\x43"
flash: 0 (pagesize: 0)
sram: 0
chipid: 0x0000
descr: unknown device
this tool shows serial of st-links and there is option called openocd. When I put hla_serial "\x36\x3f\x65\x06\x4b\x46\x32\x36\x13\x50\x06\x43" in file then it works for me. Your way does not. It also does not work in command line given as argument. It works only as I described in cfg file
The format of the configuration file seems to have changed recently. The following applies for Open On-Chip Debugger 0.10.0+dev-00634-gdb070eb8 (2018-12-30-23:05).
Find out the serial number with lsusb, st-link, or with ls -l /dev/serial/by-id. The latter yields (with two STLink/V2.1 connected):
total 0
lrwxrwxrwx 1 root root 13 Nov 30 14:31 usb-STMicroelectronics_STM32_STLink_066CFF323535474B43125623-if02 -> ../../ttyACM0
lrwxrwxrwx 1 root root 13 Dec 30 23:55 usb-STMicroelectronics_STM32_STLink_0672FF485457725187052924-if02 -> ../../ttyACM1
The specification on the .cfg-file is now plain hex. Do not use the C string syntax any longer. For selecting the latter device, simply write:
#hla_serial "066CFF323535474B43125623"
hla_serial "0672FF485457725187052924"
I have a requirement that is accessing GPIO with ubuntu 14.04LTS.
Below information is my device information:
OS:Ubuntu 14.04 LTS 64bits
CPU:Intel® Celeron(R) CPU J1900 # 1.99GHz × 4
And bleow link is datasheet and driver code
code and datasheet here.
First I was checked the chip is it8785, and GPIO port is 32 to 39.
PIN of port GPIO 32 is 117, so I type the command:
echo 32 > /sys/class/gpio/export
and
echo 117 > /sys/class/gpio/export
but both show the error "bash - echo: write error: invalid argument"
I don't have any idea for this, so I contect with manufacturer.
They told me that if i want access GPIO, I must direct access CPU address like :
GPIO PORT Adderss
32 0xfed0e388
33 0xfed0e368
34 0xfed0e318
35 0xfed0e378
36 0xfed0e308
37 0xfed0e398
38 0xfed0e328
39 0xfed0e3A8
I have googled for a while, quantity of data are rarly.
It's thanksful for any advice.
Can you try and use sudo while exporting and see if the gpio could exported.
As the manufacturer has provided with register address you can map them to user space and access. On how to access them in user space you can have a look at dev2mem. Hope that helps.
I am using noble & bleno via node.js to connect to a BLE peripheral from Rasbian, yet something goes wrong and the connection can not be made. I tried multiple different BLE dongles and they all fail the same way. Currently I have a CSR 4.0 attached.
The connections works just fine when being made from OS X, iOS or Android.
Here is the HCI Dump:
2015-11-22 18:36:54.732907 < HCI Command: LE Create Connection (0x08|0x000d) plen 25
bdaddr 00:12:6F:6B:C7:32 type 0
interval 96 window 48 initiator_filter 0
own_bdaddr_type 0 min_interval 6 max_interval 12
latency 0 supervision_to 200 min_ce 4 max_ce 6
2015-11-22 18:36:54.734511 > HCI Event: Command Status (0x0f) plen 4
LE Create Connection (0x08|0x000d) status 0x0c ncmd 1
Error: Command Disallowed
Now when I try a connection via hcitool lecc or gatttool the connection is made - yet trying to write characteristic values fails with Characteristic Write Request failed: Attribute requires authentication before read/write. Is this related?
I am on Linux raspberrypi 4.1.13+ #826 PREEMPT Fri Nov 13 20:13:22 GMT 2015 armv6l GNU/Linux
Unfortunately even security-level high or medium didn't help.
The issue was, that I had a connection from a Central (RPi is Peripheral) and I wanted to connect to another Peripheral, which would put the RPi into Central mode. Apparently this doesn't work with BlueZ.
So I ended up with using 2 Bluetooth Dongles.
If you are looking for another OS: Mac OS X does support this though.
Also I was told that Bluetooth 4.1 Dongles might work with this.
I closed SWD and JTAG by acident so that I can't download new program into developboard by j-Link.Then I try using j-flash ARM to erase chip, and error comes like this:
Connecting ...
- Connecting via USB to J-Link device 0
- J-Link firmware: V1.20 (J-Link ARM V8 compiled Dec 1 2009 11:42:48)
- JTAG speed: 2000 kHz (Auto)
- Initializing CPU core (Init sequence) ...
- Executing Reset (0, 0 ms)
- Initialized successfully
- JTAG speed: 2000 kHz (Auto)
- Connected successfully
Reading entire flash chip ...
- 64 sectors, 1 range, 0x8000000 - 0x800FFFF
- ERROR: RAM check failed # address 0x20000000.
- ERROR: Write: 0x03020100 07060504
- ERROR: Read: 0xAAAAAAAA AAAAAAAA
- ERROR: (0 bytes of RAM have been checked successfully)
- ERROR: Failed to read back target memory
Disconnecting ...
- Disconnected
I don't know how to use BOOT0 and BOOT1 to get into ISP mode. BOOT0 is connected to GND.
Post some information about your environment.
Are you using IAR EWARM? If you're not, you should download the size-limited trial version. Then, load one of the basic program examples, and try to flash it to your board.
What board are you using? And what do you mean you "closed" SWD and JTAG? I'm not sure what that refers to...jumpers? options window?
Help us out here.