PCIe Configuration Space vs ECAM - pci

Question

Is the PCIe ECAM exactly the same as the "PCI-Compatible Configuration Registers" only mapped to memory instead of I/O?
It seems to me that PCIe uses the same Configuration Mechanism as conventional PCI: [1]
| 31 | 30 - 24 | 23 - 16 | 15 - 11 | 10 - 8 | 7 - 2 | 1 - 0 |
| Enable | Reserved | Bus Nr | Device Nr | Function Nr | Register Nr | 00 |
But in PCIe you can use the reserved bytes to address more registers of a function.
Is this correct?
In section 7.2.1 [2] the ECAM is defined as:
| 27 - 20 | 19 - 15 | 14 - 12 | 11 - 8 | 7 - 2 | 1 - 0 |
| Bus Nr | Dev Nr | Function Nr | Ext. Register Nr | Register Nr | Byte Enable |
It looks very similar to the conventional configuration.
Just the reserved bits are shifted to the register number which they extend in PCIe.
But I can use them like the old one? Only address them in memory space not IO space?
[1] https://wiki.osdev.o/PCI#Configuration_Space_Access_Mechanism_.231
[2] in PCI Express Base Specification, Rev. 4.0 Version 1.0

Answer 1

You're mixing apples and oranges in your comparison. The first address decoding is provided by a host bridge component on PC-AT architecture systems (*). It's a way of using the Intel processor's I/O address space to interface to the PCI bus configuration space mechanism. It can also be used on a PCIe system, because the PCIe host bridge component provides the same interface to PCIe devices. However, everything below the host bridge is implemented quite differently between PCI and PCIe.
Meanwhile the second decoding scheme you showed can only be used within the memory-mapped block through which PCIe provides access to its extended configuration space. And only after that block has been mapped into the physical address space in a system-dependent way.
So while they have a similar function, no, you cannot use them in the same way. You can:
Access the first 256 bytes of any PCI or PCIe device's configuration space using the first mechanism, but you must use the first addressing scheme, OR
Access the entire extended configuration space of any PCIe device using the second mechanism (including the first 256 bytes), but then you must use the second addressing scheme.
(*) The "I/O space interface to PCI bus configuration via 0xCF8 / 0xCFC" really is part of the Intel / PC-AT architecture. Other system architectures (MIPS for example) don't have separate I/O address spaces, and host bridges designed for them have different mechanisms to generate PCIe configuration space accesses (or they simply use the memory-mapped mechanism directly).