https://www.youtube.com/watch?v=eMCU7ccBkk4
in this video, if there is 2^n * m bit memory, m means word size.
and as far as I know, when we calculate the memory size of 32-bit OS, we calculate like this => 2^32 * 1 byte(8bit) = 4GB. in 32-bit OS, 32 means word size. But according to the formula above, m = 8, so word size should be 8. it seems contradictory. what is wrong? what am i missing?
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Given a disk block has the size of 4096M formatted to FAT. The size of each block is 64K. Calculate the size of the FAT table.
My solution:
Number of blocks = disk size / block size = (4096 * 2^20) / (64 * 2^10) = 2^16 blocks.
Assume using FAT16, since we have 2^16 blocks -> have 2^16 entries, each entry needs to store 16 bits.
=> Size of FAT table = 2^16 * 16 = 2^20 bits = 128KB.
I'm preparing for the final exam and the funny thing is that my teacher told me to self-study virtual memory so I'm not sure that my solution and explanation are correct or not. Please help me point out if I'm doing wrong. Thanks for reading.
I've already had the answer to this question and found out I was correct. Thank you and peace out!
How can I find DRAM row buffer size programmatically or by using already existing tools in say a *nix system ?
As an example, with a Kingston DDR4, I executed the following commands (you might need to install some packages) :
sudo modprobe eeprom
decode-dimms
These commands, among many information, give me the characteristics of my DDR stick:
---=== Memory Characteristics ===---
Maximum module speed 2132 MHz (PC4-17000)
Size 16384 MB
Banks x Rows x Columns x Bits 16 x 16 x 10 x 64
SDRAM Device Width 8 bits
Ranks 2
Rank Mix Symmetrical
AA-RCD-RP-RAS (cycles) 14-14-14-35
Supported CAS Latencies 16T, 15T, 14T, 13T, 12T, 11T, 9T
Rows and columns are actually number of address bits (you can check the decode-dimms source at https://fossies.org/linux/i2c-tools/eeprom/decode-dimms, and understand what the code is doing when you look at the DDR4 SPD information: https://en.wikipedia.org/wiki/Serial_presence_detect#DDR4_SDRAM)
Thus, if we have 10 column bits, we have 1024 columns (2^10), where each column is composed of the module width (64 as per the data above, represented as "bits"). Since we can also see that the SDRAM device width is 8x, we can deduce that the DIMM locksteps 8 SDRAM chips (those black boxes you see in your DRAM stick) to get that total width of 64 bits.
The row buffer size in my DDR4 is, therefore, 64 bits * 1024 columns = 65536 bits wide (8192 Bytes). Row buffer sizes in DDR3 and DDR4 are mostly this length, but new architectures such as HMC and HBM have different sizes.
So, in one short commandline, to return in bits (just divide by 8 to get bytes):
decode-dimms | grep "Columns x Bits" | awk -F 'x' '{print (2^$(NF-1))*$NF}
PS: mind you, this handles a single DIMM. if you have multiple DIMMS decode-dimms might return information for multiple modules.
a) Suppose there is a RAM of size 4GB installed in an intel Core i5 computer. If the system supports 64bit word then how many words can be stored in the RAM? Also how many bits will be required to address each Word uniquely?
There are a lot of variables to this question. How big are the words? How much RAM does Microsoft let Word use before it starts swapping data in a pagefile? Is any compression used?
If we assume that Word has access to all 4GB of RAM (the OS, and Word aren't using any in this situation), that there is no pagefile to dump to, and no compression going on in the background, we can do some simple math to find out. We know that typically a single ascii character takes up 1 byte of memory, and that there are 1024 bytes in a KB, 1024 KB in a MB, and so on. So, we just multiply until we get to 4GB worth of bytes. 1024 Bytes X 1024 KB X 1024 MB X 4 GB = 4,294,967,296 ascii characters.
Coincidentally, that's the maximum number of possible 32-bit addresses in 32bit systems, and why 32bit systems were unable to support more than 4GB of RAM without Physical Address Extension (PAE). With so little RAM, it doesn't matter that the program is 64bit, it just means it can handle addressing and integers larger than that if the RAM is available.
I hope that helps you in some way! I'm kind of concerned that you are having to worry about the maximum number of words that can be stored in 4GB.
I'm learning the concept of directed mapped cache, but I don't get it how to get cache memory size and main memory size by using block size. (The unit is bytes.) the given values are 2^3 words = 2^5 bytes of block size, 4 bits of tags(0000~1111) and 3 bits of the index(000~111).
the questions >>
what's the size of cache memory and main memory in each?
and which address do we insert in each data part?
I already tried to separate the part tag and the cache index. I insert the tag on 3 upper order bits and insert the cache index(29 bits) on the remaining space. I got the main memory size, 4GB, and the cache size, 2^29 bytes. but I think something is wrong. I feel that I don't understand the concept of this.
Your answer is incorrect, because you are assuming address is 32 bits and it is byte addressable, hence the 4GB memory size. This is not true and we must first compute these values.
8 words = 32 bytes = block size
So offset=3 bits (to address 8 words in a block)
and word size=4 bytes/word (32 bytes/8 words)
We have now the width of an address: 4 bits (tag) + 3 bits (index) + 3 bits (offset)= 10 bits.
With 10 bits address, main memory is 2^10 words=2^12 bytes=4kB
Cache has 8 blocks (3 bits index), each block has 32 bytes and cache size=8*32 bytes=256B.
I have a homework question during studying for a test:
You have a new device with logic addresses space of 32 bit and physical addresses space of 34 bit. Size of page is 8KB (2^13 B). Calculate size of page table (of single level).
There are 2^32 / 2^13 = 2^19 entries. And what is the size of entry, I have to assume that it's 4B or I have a way to calculate it?
As you have already mentioned no. of enteries will be 2^32/2^13, but the page size can be anything (predefined), also you can have operating systems supporting multiple page sizes, hence to best of my understanding you can't calculate the page size through this as it is predefined and virtual memory can be any big.
There are 2^19 entries now each of these entry will be 32 Bit wide so space occupied = (2^19) * (32) Bits