so, suppose I have a file file.c, and a file anothr.c. I would like to set the compilation command for each of those files separately, say: gcc -Wall -O3 -o f file.c, and gcc -Wall -std=c99 -o a another.c. How can I set the gcc command for that buffer so that every time I open it, it knows how to compile it? Is there something with the // -*- directive or something like that? Thanks.
Yes, you can use the directive in the file, and also set other value. Try this in line one or two:
// -*- compile-command: "gcc -Wall -O3 -o f file.c" -*-
and then re-load the file with C-x v so that the setting takes effect.
I sometimes set things like c-indent-level: 4; c-basic-offset: 4; in there too.
What you're looking for are called file local variables, or sometimes just "local variables", per the in-comment declarative format described here.
In addition to the syntax given in Dirk's answer, you can write a "local variables" block at the end of your file:
/* Local Variables: */
/* compile-command:"gcc -Wall -O3 -o f file.c" */
/* End: */
You can use the interactive function add-file-local-variable to help maintain this list if you don't want to type each entry manually.
Related
A project I am trying to compile has this command:
cc -xc++ -o/dev/null -lc++ -shared
However I am using PowerShell, which has no notion of /dev/null:
PS C:\> cc -xc++ -o/dev/null -lc++ -shared
C:/msys2/mingw64/bin/../lib/gcc/x86_64-w64-mingw32/10.2.0/../../../../
x86_64-w64-mingw32/bin/ld.exe: cannot open output file /dev/null.exe: No such
file or directory
I tried using -o$null, but it just creates a file $null.exe. I also tried this:
PS C:\> cc -xc++ -o $null -lc++ -shared
cc.exe: fatal error: no input files
Is PowerShell able to handle this use case? Alternatively, it seems the purpose of the test is to just check if libc++ exists. Is another way available to do that?
It appears the issue is specific to GCC. If I get Clang, the same command
works with nul:
cc -xc++ -onul -lc++ -shared
but if I try the same thing with GCC, I get this:
C:/msys2/mingw64/bin/../lib/gcc/x86_64-w64-mingw32/10.2.0/../../../../
x86_64-w64-mingw32/bin/ld.exe: nul.exe: final close failed: file truncated
I have posted bug 97574.
I use the Verilog mode from emacs.
My question is:
What is full syntax of command that includes verilog-library-directories ?
emacs --batch f.sv -q --eval='(setq-default verilog-typedef-regexp
".*_t$")' -f verilog-batch-auto
For including verilog libraries I use the following comment at the end of the file:
// verilog-library-flags:("-y ../rtl")
I think then you can reuse this syntax for command line.
I've got a Makefile.mak where I optionally create a test.exe or a DLL from my C-based source code. I'm using CL.EXE and NMAKE.
I'd like to modify my CFLAGS macro like this when the target is TEST.EXE:
CFLAGS = $(CFLAGS) -DMAIN
And, of course, I use this in my C code:
#ifdef MAIN
... int main()... yada yada
#endif
I had tried
!IF $# == "test.exe"
but it crashed out and doesn't work logically since the $#, target, isn't deterministic in that part of the makefile.
The logical place to define the additional macro is when defining the target but I don't see how to do that without NMAKE interpreting it as DOS command.
test.exe: test.obj
CFLAGS = $(CFLAGS) -DMAIN
$(LINKER) /out:$# $(LIB) $*.obj $(LIBS)
It'd be easier with gmake, I know. I don't have that option.
I will present two solutions: one which does what you request, namely modifying CFLAGS based on the target, and a second one which may be a better approach.
Suppose you have a file multiply.c:
#include <stdio.h>
int multiply(int a, int b) {
return a * b;
}
#ifdef MAIN
int main() {
printf("Unit test: multiply(2, 3) = %d\n", multiply(2, 3));
}
#endif
which you would like to add to a static library my_lib.lib, and also use as a stand-alone unit test.
One standard way of adding -DMAIN to CFLAGS is to use NMAKE recursively. The second invocation of NMAKE could use a different makefile or, as as presented here, use the same makefile with a flag to prevent an infinite recursive loop.
TARGETS = my_lib.lib multiply.exe
CFLAGS = -W4 -O2 -nologo -Zi
all: $(TARGETS)
my_lib.lib: multiply.obj
my_lib.lib:
lib -nologo -out:$# $**
!ifndef RECURSE
multiply.exe:
nmake -nologo CFLAGS="-DMAIN $(CFLAGS)" RECURSE= $#
!endif
multiply.obj: .FORCE
.FORCE:
If RECURSE is defined, the built-in rule is used to create the test program multiply.exe.
This solution works. But it requires that multiply.obj be remade every time it is used, because there are two versions of it floating around: one with a main and one without.
The second solution distinguishes between these object files.
TARGETS = my_lib.lib multiply.exe
CFLAGS = -W4 -O2 -nologo -Zi
all: $(TARGETS)
my_lib.lib: multiply.obj
multiply.exe: $*.TEST_obj
my_lib.lib:
lib -nologo -out:$# $**
multiply.exe:
link -nologo -out:$# $**
.c.TEST_obj:
$(CC) -DMAIN $(CFLAGS) -c $< -Fo$#
This gives:
>nmake -nologo
cl -W4 -O2 -nologo -Zi /c multiply.c
multiply.c
lib -nologo -out:my_lib.lib multiply.obj
cl -DMAIN -W4 -O2 -nologo -Zi -c multiply.c -Fomultiply.TEST_obj
multiply.c
link -nologo -out:multiply.exe multiply.TEST_obj
Trying to create a .exe file directly from the .c file, as in:
.c.exe:
$(CC) -DMAIN $(CFLAGS) $<
does not work, because this still creates a .obj file which clobbers the other version.
Edit: .SUFFIXES: .TEST_obj does not seem to be needed.
I am trying to make an External Tool in Eclipse which requires several file names as inputs. However, I need to edit the output from the variable to exclude the file extension.
My arguments look as follows:
makeindex ${selected_resource_name}.nlo -s nomencl.ist -o ${selected_resource_name}.nls
The output from this compiles as follows:
makeindex filename.tex.nlo -s nomencl.ist -o filename.tex.nls
However, I would like to remove the .tex extensions, so the command compiles as
makeindex filename.nlo -s nomencl.ist -o filename.nls
Is this possible? And if so, how can I do this from within Eclipse?
From what i am seeing it looks like you are trying to replace '.tex' with '.nlo'. You could use substring to specify the name minus the last four characters (.tex). And do the rest as you were.
Example:
$new_name = substr(selected_resource_name, 0, -4);
makeindex ${new_name}.nlo -s nomencl.ist -o ${new_name}.nls
This should return your desired result.
In the code below, I would like the value of THE_VERSION_STRING to be taken from the value of the environment variable MY_VERSION at compile time
namespace myPluginStrings {
const char* pluginVendor = "me";
const char* pluginRequires = THE_VERSION_STRING;
};
So that if I type:
export MY_VERSION="2010.4"
pluginRequires will be set at "2010.4", even if MY_VERSION is set to something else at run time.
UPDATE: (feb 21) Thanks for your help everyone. It works.
As I'm using Rake as a build system, each of my CFLAGS is a ruby variable. Also the values need to end up in quotes. Therefore the gcc command line for me needs to look like this:
gcc file.c -o file -D"PLUGIN_VERSION=\"6.5\""
Which means this is in my Rakefile:
"-D\"PLUGIN_VERSION=\\\"#{ENV['MY_VERSION']}\\\"\""
If I recall correctly, you can use the command line parameter -D with gcc to #define a value at compile time.
i.e.:
$ gcc file.c -o file -D"THE_VERSION_STRING=${THE_VERSION_STRING}"
In the code below, I would like the value of THE_VERSION_STRING to be taken from the value of the environment variable MY_VERSION at compile time
No, you can't do it like this. The only way to extract environment variables is at runtime with the getenv() function. You will need to explicitly extract the value and copy it to pluginRequires.
If you want the effect of a compile-time constant, then you'll have to specify the definition on the compiler commandline as Seth suggests.