What is the number of clock cycles required in the given sequence of Instruction using 5- stage pipelined CPU? - cpu-architecture

Question

A 5 stage pipelined CPU has the following sequence of stages:
IF – Instruction fetch from instrution memory.
RD – Instruction decode and register read.
EX – Execute: ALU operation for data and address computation.
MA – Data memory access – for write access, the register read at RD state is
used.
WB – Register write back.
Consider the following sequence of instructions:
I1: L R0, loc 1 ; R0 <=M[loc1]
I2: A R0, R0 1 ; R0 <= R0 + R0
I3: S R2, R0 1 ; R2 <= R2 - R0
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of
instructions starting from the fetch of I1?
So here's my solution.
1 2 3 4 5 6 7 8 9 10 11 12 13
I1: IF RD EX MA WB
I2: IF - - - RD EX MA WB
I3: IF - - - - - - RD EX MA WB
In this way I'm getting total 13 cycles. I'm assuming that since operand forwarding is not explicitly mentioned in the question. So register will be only available after WB stage. But option are following:
A. 8
B. 10
C. 12
D. 15

Answer 1

For Write access the register read at RD stage is used- this means if we cannot operand forwards a value to MA stage. So, we can assume operand forwarding can be done for other stages.
With data forwarding:
T1 T2 T3 T4 T5 T6 T7 T8
IF RD EX MA WB
-IF RD - EX MA WB
--IF - RD EX MA WB
Hence, answer will be 8.
http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/forward.html

Answer 2

The given problem is based on structural hazard because of the below line
" MA – Data memory access – for write access, the register read at RD state is used "
and not on data dependency although it seems to have data dependency. And hence, nothing is mentioned about data forwarding in the question.
Structural hazard is for the load instruction. And hence the execution of the next instruction cannot start until the execution of the first instruction, because the effective address of the memory location referred by M[loc1] will be calculated only during the execution phase of the pipeline. So till then the bus will not be freed and hence the second instruction cannot be fetched. Thus second instruction will take extra 2 clock cycles.
And the third instruction cannot start execution till the first instruction successfully loads the data to register R0. Which results the third instruction to have 3 more clock cycles.
Hence, total clock cycles = (CC for I1) + (CC for I2) + (CC for I3)
= 5 + 2 + 3
= 10 clock cycles