Why is this Mutex solution incorrect? - mutex

There are 2 processes P1 and P2 that can enter the Critical Section.
Mutex Solution Requirements:
A Mutex Zone - (Critical Section) that can only hold one process maximum.
No Mutual Blocking - a process outside the critical section cannot block a process inside it.
No Starvation - a process interested in entering the critical section must not have to wait forever.
Success without Contention - a process interested in entering the critical section must succeed in doing so if there are no other processes interested.
Why is the below code an incorrect solution to the Mutual Exclusion problem?
i.e. which requirement does it not satisfy?
C1 and C2 are initialised to 1.
P1: LOOP
Non-Critical Section
LOOP UNTIL C2 = 1 END_LOOP;
C1 := 0;
Critical Section
C1 := 1;
END
P2: LOOP
Non-Critical Section
LOOP UNTIL C1 = 1 END_LOOP;
C2 := 0;
Critical Section
C2 := 1;
END

To interpret the question with the best of intentions, I would have to assume that each read or write is deemed to be atomic and well-ordered. Then it makes more sense.
The problem you have here is that the inner loop in each process can independently complete. Those loops are the "wait for my turn" part of the mutex.
However, the terminating of that loop and the following assignment (which would stop the other loop from terminating) are not atomic. We therefore have the following possible scenario:
P1: exit wait loop because C2 is 1
P2: exit wait loop because C1 is 1
P2: set C2 to 0
P2: enter critical section
P1: set C1 to 0
P1: enter critical section
The above violates that first requirement of having a Mutex Zone. Conditions that lead to such a violation are commonly known as a race condition.
You could also expect one process to starve the other. There is a possibility that P2 will always execute its critical section and acquire the lock again before P1 (who is waiting for the lock) gets a slice of CPU time. The control variable C2 would therefore always be 0 as seen by P1. Or at least, may be that way for a disproportionate number of slices.
P2: exit wait loop because C1 is 1
P2: set C2 to 0
P1: spin on C2 != 1 for entire time slice
P2: enter critical section
P2: set C2 to 1
P2: exit wait loop because C1 is 1
P2: set C2 to 0
P1: spin on C2 != 1 for entire time slice
P2: enter critical section
P2: set C2 to 1
P2: exit wait loop because C1 is 1
P2: set C2 to 0
P1: spin on C2 != 1 for entire time slice
...
Except in some environments, it's unlikely that P1 would be starved forever. But since P1 has asserted that it is waiting, it should not expect P2 to get multiple cracks at the critical section before it gets a turn.
This might also be a violation of the Success Without Contention requirement, but that's hard to argue really. But I would suggest that if P2 is no longer running, then consider what state C2 might be left in, and why P1 should need to know about P2 at all.

Related

MATLAB: Efficient way to find a goal value based on two variables

I have a system from which I need to attain a defined goal G from a starting value G0 by adjusting two actuators A and B with initial values A0 and B0 whose values vary dependently i.e. if I adjust A, B will change slightly but needs to be kept constant at B0.
To attain G I need to move A from -pos to +pos in steps of 1 and after each step, check if abs(G-G0) <2 and also check if B has deviated from B0 i.e. abs(B-B0)<2. If it has I need to adjust its position in the range -pos1 to +pos1 in steps of 1 until B=B0.
The iteration stops when I find a value of A which satisfies G (G=80 in my example below).
At the moment I am using a for loop:
Let's suppose
G=80;
G0=73;
pos0=50;
pos=5;
pos1=7;
for posA=-pos+pos0:1:pos0+pos
A=moveA(posA); %moveA represents the transfer function that takes posA and moves actuator A, returning value A
if abs(G-G0)>2 && abs(B-B0)> 2
for posB=-pos+pos1:1:pos1+pos
B=moveB(posB); %moveB represents the transfer function that takes posB and moves actuator B, returning value B
if abs(B-B0)> 2
break;
else
continue
end
end
else
fprintf(' %i is the value of A to reach goal',A)
break
end
end
I'm looking for suggestions to optimize and speed up this code in MATLAB, as currently it takes a long time iterating.

usage of $past macro in system verilog for a signal to high

I am a starter in system verilog.
I want to check on a falling edge of the signal whether it is high for the past 'n' number of cycles. Usage of ##n cycles doesn't work for me.
logic x,y;
x & y -> ##2 $past(y) -> $fell(y); this doesn't seem like working
with the condition of x & y, what I am checking is at the falling edge of 'y' the signal 'y' is high for past 2 cycles after the condition x& y is met
Hi and welcome to SVA.
In my answer i shall assume that you have defined a clock and are using this in your definition of "falling edge"
There are a few issues with your code and problem description. I only enumerate these to help with issues in the future:
- $past is not a macro but a system function
- You are not using the correct SVA implication operator. "->" is a blocking event trigger. The overlapping implication operator I guess you are after is |->
- ##2 $past(y) will actually insert a delay of 2 cycles, and then check that the past value of y was high. Really, you are checking that y is high one cycle after your initial trigger.
I am also not quite sure what your trigger condition is meant to be - x && y will spawn a property thread if both x and y are high. In fact, it won't trigger on a negedge of y.
In the following code I attempt to code up the SVA to your spec as I understood it. You can use a simple function to ensure that preceding n cycle, y was high. Feel free to replace $fell(y) with any trigger as required.
function bit y_high_preceding_n_cycles(int n)
for(int i = 1; i < n; i++) begin
// check if y wasnt high i cycles ago, just return 0
if (!$past(y, i, , #(posedge clk))) return 0;
end
return 1;
endfunction
prop_label: assert property($fell(y) |-> y_high_preceding_n_cycles(n));
This will check that on detection of $fell(y), y was high the preceding n cycles. Note that the iteration of the for loop i==1 will by definition be redundant (as trigger on $fell(y) i.e. definitely $past(y) == 1 holds assuming no Xs).
Hope this helps.

Unicode BIDI (UBA): R RLI R; Why should RLI stay on level 0

implementing isolater logic for the BIDI got me stuck again. Given the following test case.
#Levels: 1 0 1
#Reorder: 0 1 2
R RLI R ; 2 # LTR flag
\____/ \_/ (my run sequences)
Here is my current understanding:
After processing rules X1-X8 you end up with levels 0 0 1 which will convert to two isolated run sequences.
As far as I can tell, rules W1-W7 should not apply to any characters.
Rule N1 however will raise the level of the RLI to 1 as it is an NI between two strong types, the R and the eos of the first sequence.
Rule I1/2 will then push the first R to level 1.
Rule L1 could lower the level of an RLI but does not apply here.
How is that, that the RLI should end up on level 0.
Same problem with similar tests, just invthe opposite direction.
#Levels: 2 1 2
#Reorder: 2 1 0
L LRI L; 4
Sadly http://unicode.org/cldr/utility/bidi.jsp does not implement the latest algorithm including the RLI/LRI.
Any advice welcome :) thank you.
Okay the issue was that Rule N1 should not have been applied since the eos is of type L and not R.
I have missed the Note at X10 stating that: ...and if there is none or the last character of the sequence is an isolate initiator (lacking a matching PDI), with the paragraph embedding level."

Distributivity of 'or' operation in SVA

Given the two properties P1 = (R1 or R2) |-> P and P2 = (R1 |-> P) or (R2 |-> P), where R1 and R2 are sequences and P is a property, is it correct to say that P1 is equivalent to P2?
I did the calculations based on the definitions of tight and neutral satisfiability in Annex F of the LRM and they came up as being equivalent. (I don't want to exclude the possibility of me making a mistake somewhere.)
I ask, because I've seen the two being handled differently by simulation tools.
I did the math again today and the two are not equivalent. There are cases where the property-or form passes, but where the sequence-or form would fail.
A simple example of this would be the properties:
P1 = (1 or (1 ##1 1)) |-> 1
P2 = (1 |-> 1) or (1 ##1 1 |-> 1)
P2 is strongly satisfied by any one clock cycle long trace, aside from ⊥. P1 can never be satisfied by traces shorter than two clock cycles. (This comes out when plugging the conditions of property satisfaction for both forms into the definition of strong satisfaction.)
What this means in plain English is that both threads started in P1 (the one for the R1 part and the one for the R2 part) need to complete until an assertion of this property is deemed successful. For P2, though, only one of the properties is required to "mature" and at this point, the other property's attempt will be discarded.
This seems a bit strange at first glance and not so intuitive, but it stems out of the formal semantics for SVAs. I guess, but I'm not sure, that P3 = first_match(R1 or R2) |-> P is equivalent to P2. One would need to do the math.

What is the number of clock cycles required in the given sequence of Instruction using 5- stage pipelined CPU?

A 5 stage pipelined CPU has the following sequence of stages:
IF – Instruction fetch from instrution memory.
RD – Instruction decode and register read.
EX – Execute: ALU operation for data and address computation.
MA – Data memory access – for write access, the register read at RD state is
used.
WB – Register write back.
Consider the following sequence of instructions:
I1: L R0, loc 1 ; R0 <=M[loc1]
I2: A R0, R0 1 ; R0 <= R0 + R0
I3: S R2, R0 1 ; R2 <= R2 - R0
Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of
instructions starting from the fetch of I1?
So here's my solution.
1 2 3 4 5 6 7 8 9 10 11 12 13
I1: IF RD EX MA WB
I2: IF - - - RD EX MA WB
I3: IF - - - - - - RD EX MA WB
In this way I'm getting total 13 cycles. I'm assuming that since operand forwarding is not explicitly mentioned in the question. So register will be only available after WB stage. But option are following:
A. 8
B. 10
C. 12
D. 15
For Write access the register read at RD stage is used- this means if we cannot operand forwards a value to MA stage. So, we can assume operand forwarding can be done for other stages.
With data forwarding:
T1 T2 T3 T4 T5 T6 T7 T8
IF RD EX MA WB
-IF RD - EX MA WB
--IF - RD EX MA WB
Hence, answer will be 8.
http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/forward.html
The given problem is based on structural hazard because of the below line
" MA – Data memory access – for write access, the register read at RD state is used "
and not on data dependency although it seems to have data dependency. And hence, nothing is mentioned about data forwarding in the question.
Structural hazard is for the load instruction. And hence the execution of the next instruction cannot start until the execution of the first instruction, because the effective address of the memory location referred by M[loc1] will be calculated only during the execution phase of the pipeline. So till then the bus will not be freed and hence the second instruction cannot be fetched. Thus second instruction will take extra 2 clock cycles.
And the third instruction cannot start execution till the first instruction successfully loads the data to register R0. Which results the third instruction to have 3 more clock cycles.
Hence, total clock cycles = (CC for I1) + (CC for I2) + (CC for I3)
= 5 + 2 + 3
= 10 clock cycles