How to use modport and What is the benefit to instanciate between interface and DUT in systemverilog? - system-verilog

Question

I'm verilog user and unfamiliar with systemverilog.
I have found what to used modport and instanciate between DUT and interface in systemverilog.
But I don't no why use the modport and how to use and interconnect between interface and DUT in systemverilog?

Answer 1

Modport is short for module port. They allow for the definition of different views of the signals within the interface. In many cases, just two modports, or views, are needed - One for the source-side of the interface, and one for the sink-side. A simple example is below:
interface simple_if ();
wire we;
wire wdata;
wire full;
// source-side view
modport src (
output we,
output wdata,
input full
);
// sink-side view
modport snk (
input we,
input wdata,
output full
);
endinterface
The interface can be used to connect two module instances together, and which view, or modport to use can be specified at each module instance using the dot notation. Example below using the interface definition above:
module top();
// first, instantiate the interface
simple_if simple_if ();
// source-side module instantiation
src_side_module u_src_side_module (
.clk (clk),
.rstl (rstl),
.if(simple_if.src) // .src specifies the modport
);
// sink-side module instantiation
snk_side_module u_snk_side_module (
.clk (clk),
.rstl (rstl),
.if(simple_if.snk) // .snk specifies the modport
);
endmodule
Couple other notes:
The clocks and resets can also be passed around inside the interface.
Alternatively, the modport can be specified down in the module where you specify the IO, like this:
module src_side_module (
input wire clk,
input wire rstl,
simple_if.src if
);
....
Hope this helps.