Creating a lookup table in CHISEL - scala

Question

I am trying to create a lookup table in Chisel of width 72 bits and 1024 entries. These 1024 entries are stored separately in a file, which I read into my code. The code I have written so far is:
import Chisel._
import scala.io.Source._
module mdlNm {
// function to read entries from file 'omega_i.dat'
def fileRead() = {
val fileIn = fromFile("omega_i.dat").getLines.toList
val num = fileIn.map(i => BigInt(i, 16)) // converting the hexadecimal entries from string to BigInt
val uInt = num.map(i => UInt(i, width = 72)) // converting BigInt entries to UInt of width 72
ROM (uInt) // Chisel construct for creating an LUT for fixed entries
}
// The above LUT is later read as follows:
val in = Bits("h123") // Any 10-bit input to the LUT
val lutOut = fileRead().read(in) // Value read from the LUT
}
The above code throws up many errors of the form:
cppBackend//sinCos.cpp:2407:23: error: ‘T1785’ was not declared in this scope
{ T425.put(1018, 0, T1785[0]); T425.put(1018, 1, T1785[1]);}
^
cppBackend//sinCos.cpp:2408:23: error: ‘T1786’ was not declared in this scope
{ T425.put(1019, 0, T1786[0]); T425.put(1019, 1, T1786[1]);}
^
cppBackend//sinCos.cpp:2409:23: error: ‘T1787’ was not declared in this scope
{ T425.put(1020, 0, T1787[0]); T425.put(1020, 1, T1787[1]);}
^
cppBackend//sinCos.cpp:2410:23: error: ‘T1788’ was not declared in this scope
{ T425.put(1021, 0, T1788[0]); T425.put(1021, 1, T1788[1]);}
^
cppBackend//sinCos.cpp:2411:23: error: ‘T1789’ was not declared in this scope
{ T425.put(1022, 0, T1789[0]); T425.put(1022, 1, T1789[1]);}
^
cppBackend//sinCos.cpp:2412:23: error: ‘T1790’ was not declared in this scope
{ T425.put(1023, 0, T1790[0]); T425.put(1023, 1, T1790[1]);}
However, when I change the width of uInt to any number <= 64, no such issues arise and the code works properly.
Is there an alternative way to create an LUT of the size I specified above, in Chisel? Or am I doing something wrong in the above code?
Please help.

Answer 1

In chisel3,, the current version, this would be constructed a little bit differently. VecInit is used instead of ROM
I would recommend the creation of an intermediate value lut to hold the rom created by buildLookupTable
because each call to buildLookupTable would read the file again and create another rom.
import chisel3._
import chisel3.util._
import firrtl.FileUtils
class SomeModule extends MultiIOModule {
def buildLookupTable(): Vec[UInt] = {
VecInit(FileUtils.getLines("file1.dat").map { s => BigInt(s, 16).U })
}
val lut = buildLookupTable()
// The above LUT is later read as follows:
val in = 0x123.U // Any 10-bit input to the LUT
val lutOut = lut(in) // Value read from the LUT
// rest of module
...
}
I don't know what the problem with lengths you had but I have tested the above with UInts with widths of 500 and it works fine.