In which programming language this code snippet is written? - cnc

The code is written in 1999 and controls a CNC machine. If the code snippet is not adequate to determine the language i can upload the entire file. This is the code segment:
BEGIN CONDITION +S_P0_PRES AND +N_P0__PNLTST ON EXCEPTION BEGIN
SET N_P0_STB OFF
SET N_P0_KEY(*) TO BITS(0)
SET N_P0_LTS(*) TO BITS(0)
SET ..KEY_PLS(*) TO BITS(0)
SET S_P0_KEY_PLS(*) TO BITS(0)
SET S_NCX0_FLEDS(*) TO BITS(0)
IF
:-S_P0_PRES: BEGIN
SET N_P0_ACT OFF
RETURN
END
END IF
WAIT +N_P0__PNLTST OR -S_P0_PRES
END
IF
:+N_P0_STB: BEGIN
LET ..KEY_INX = 0
REPEAT WHILE [INT(..KEY_PLS(*)) <> 0]
IF
:+..KEY_PLS(..KEY_INX): BEGIN
IF
:[..KEY_NUM(..KEY_INX) < 128]: BEGIN
IF
:-..KEY_ISF(..KEY_INX): SET N_P0_KEY(..KEY_NUM(..KEY_INX)) OFF
:+..KEY_ISF(..KEY_INX): SET .P0_NCX_FUN(..KEY_NUM(..KEY_INX)) OFF
END IF
START N_P0__NCXKEY
END
:[..KEY_NUM(..KEY_INX) < LAST(N_P0_KEY(*)) + 1]: BEGIN
SET N_P0_KEY(..KEY_NUM(..KEY_INX)) OFF
START N_P0__MAIKEY
END
:[..KEY_NUM(..KEY_INX) < LAST(.P0_NCX_FUN(*)) + 1]: BEGIN
SET .P0_NCX_FUN(..KEY_NUM(..KEY_INX) - (LAST(N_P0_KEY(*)) - 127)) OFF
START N_P0__FKEY
END
END IF

I think you're looking at APT.

Related

System Verilog- How to ensure that specific code will be executed before another?

I have the following code in my monitor:
virtual task run_phase(uvm_phase phase);
fork
begin : clock_c
forever begin
wait(vif.fact_log2_samp != fact_log2_samp_init);
for(int counter = 0; counter < 46; counter++) begin
check = 1'b0;
#(posedge vif.clk);
end
**check =1'b1;**
end// forever
end// clock_c
begin : main_0
forever begin
mon_trx = tx_lin_int_transaction::type_id::create("mon_trx");
mon_trx.fact_log_2 = fact_log2_samp_init;
**wait (vif.xn_valid == 1'b1);**
#1;
mon_trx.rand_data_xi = vif.xi;
mon_trx.rand_data_xq = vif.xq;
if (check == 1'b0)
mon_trx.check = FALSE;
else
fact_log2_samp_init = vif.fact_log2_samp;
$cast(t, mon_trx.clone());
//send transaction to scoreboard via TLM write()
ap.write(t);
wait (vif.xn_valid == 1'b0);
end// forever
end// main_0
join
endtask: run_phase
The problem is that
wait(vif.xn_valid == 1'b1);
and the code after it execute just before
check =1'b1;
(same time).
How can I ensure that the
check =1'b1;
will execute before?
I would follow the named events method, as AndresM suggested, but if you need a quick sync in the very same block with the very same trigger condition, a simple #0 might solve the issue, thou it is unreliable due to the simulation time handling reasons. Might worth a try:
begin : clock_c
...
**check =1'b1;**
...
end
begin : main_0
...
#0;
**wait (vif.xn_valid == 1'b1);**
...
end
also you can use labels for the begin-end blocks to look and read better, eg.:
begin: main_0, end: main_0 instead of end // main_o
You might want to take a look at Chapter 15 of the IEEE Std 1800-2012, where they cover in great detail every aspect related to the different interprocess synchronization and communication mechanisms that the SystemVerilog language offers. Those options are listed below (follow the hyperlinks to see a few examples and how to use each one of them):
Semaphores
Mailboxes
Named Events

The counter counts strangly

My code describes a FSM to control a traffic light. There are four states, each with a different
duration.
Whenever the counter equals 1, the counter needs one more clock to change to the next value. For example, at state1, counter is programmed to count from 4 to 1. Every value should only take one clock to
change to the next, when it does, the state is changed to the next state. But when counter equals 1, it takes two clocks to change.
My program is as follows. The counter is implemented at the bottom of the always block:
module HW3(times,A,B,clk,rst,iHand,iChang,s1);
input clk,rst;
output reg [2:0]A,B;
wire oclk;//new freq
reg [2:0] count1,count2,count3,count4;//count times
reg [2:0]times;
reg temp;//control the switch
parameter [2:0]state1=3'd0,state2=3'd1,state3=3'd2,state4=3'd3;
always#(posedge clk or negedge rst )
begin
if(!rst)
begin
s1<=state1;
A<=3'b0;
B<=3'b0;
count1<=3'd4;
count2<=3'd2;
count3<=3'd3;
count4<=3'd2;
temp<=1'b1;
end
else
begin
if(temp==1)
begin
temp<=1'b0;
case(s1)
state1:
begin
times<=count1;
A<=3'b001;
B<=3'b100;
s1<=state2;
end
state2:
begin
times<=count2;
A<=3'b010;
B<=3'b100;
s1<=state3;
end
state3:
begin
times<=count3;
A<=3'b100;
B<=3'b001;
s1<=state4;
end
state4:
begin
times<=count4;
A<=3'b100;
B<=3'b010;
s1<=state1;
end
default:
begin
A<=3'b000;
B<=3'b000;
end
endcase
end
else
begin
if(times>1)
times<=times-1;
else if(times==1)
begin
temp<=1'b1;//can't count averagely
end
end
end
end
endmodule
Modify the code at the bottom of the always clock as:
if(times>2)
times<=times-1;
else if(times==2)
begin
times=times-1;
temp<=1'b1;//can't count averagely
end
Just let the times counts to 2 ,because if let it count to 1, the program will again enter the if
block in the next clock but doesnt change the value of times ,and make the value of times=1 unchanged
for one more clock

[Verilog]Why my counter's output delays one more clock?

My partial program is as followed, it's a FSM to handle the traffic light,and the register "times" (from 4 to 1) is to compute the time that the traffic light should brighten, But whenever "times" counts to "1", the time of "times=1" is longer than other "times" about one clock.
For example:when times = 4~2,every clock will count ,but when times=1,it will take two clocks
to become times=4.
Could anybody tell me how this problem happened?
always#(posedge clk or negedge rst )
if(!rst)
begin
s1<=state1;
A<=3'b0;
B<=3'b0;
count1<=3'd4;
count2<=3'd2;
count3<=3'd3;
count4<=3'd2;
temp<=1'b1;
end
else
begin
if(temp==1)
begin
temp<=1'b0;
case(s1)
state1:
begin
times<=count1;
A<=3'b001;
B<=3'b100;
s1<=state2;
end
state2:
begin
times<=count2;
A<=3'b010;
B<=3'b100;
s1<=state3;
end
state3:
begin
times<=count3;
A<=3'b100;
B<=3'b001;
s1<=state4;
end
state4:
begin
times<=count4;
A<=3'b100;
B<=3'b010;
s1<=state1;
end
default:
begin
A[0]<=3'b000;
B[0]<=3'b000;
end
endcase
end
else
begin
if(times>1)
times<=times-1;
else if(times==1)
begin
temp<=1'b1;//can't count averagely
end
end
end

Console application via network in eiffel?

Hey I'm working in project, but i cant manage to connect from a IP not located in the same network (LAN). The code bellow works fine locally, but I cant figure out how to make work from different IP located in different locations?, and google cant see to help, any ideas?
class
RG_NETWORK_SERVER
inherit
STORABLE
NETWORK_SERVER
redefine
receive,
received,
close
end
create
make_server
feature
connections: LINKED_LIST [RG_CONNECTION]
max_to_poll: INTEGER
message_out: RG_MESSAGE
received: detachable RG_MESSAGE
poll: MEDIUM_POLLER
make_server
require
local
l_message_out: detachable like message_out
l_connections: detachable like connections
l_in: detachable like in
do
make (1337)
max_to_poll := 1
create poll.make_read_only
in.set_non_blocking
l_in := in
create l_message_out.make
message_out := l_message_out
create l_connections.make
connections := l_connections
connections.compare_objects
execute
end
process_message
local
stop: BOOLEAN
pos: INTEGER
do
from
connections.start
until
connections.after or stop
loop
if connections.item.is_waiting then
if attached {RG_MESSAGE} retrieved (connections.item.active_medium) as l_message_in then
if l_message_in.new then
connections.item.set_client_name (l_message_in.client_name)
create message_out.make
message_out.set_client_name (l_message_in.client_name)
message_out.extend (l_message_in.client_name)
message_out.extend (" has just joined the server%N")
elseif l_message_in.over then
poll.remove_associated_read_command (connections.item.active_medium)
connections.remove
create message_out.make
message_out.set_client_name (l_message_in.client_name)
message_out.extend (l_message_in.client_name)
message_out.extend (" has just gone%N")
stop := True
else
message_out := l_message_in.deep_twin
message_out.put_front (" has just sent that :%N")
message_out.put_front (message_out.client_name)
message_out.put_front ("-> ")
end
pos := connections.index
-- l_message_in.print_message
message_out.print_message
broadcast
connections.go_i_th (pos)
-- Post status to client
create message_out.make
message_out.extend ("Got it! %N")
message_out.independent_store (connections.item.active_medium)
end
end
if not stop then
connections.forth
end
end
end
broadcast
local
client_name: detachable STRING
do
client_name := message_out.client_name
if client_name /= Void then
from
connections.start
until
connections.after
loop
if connections.item.client_name /~ client_name then
message_out.independent_store (connections.item.active_medium)
end
connections.forth
end
end
end
receive
do
in.accept
if attached {like outflow} in.accepted as l_outflow then
l_outflow.set_blocking
new_client (l_outflow)
end
from
connections.start
until
connections.after
loop
connections.item.initialize
connections.forth
end
poll.execute (max_to_poll, 1000)
end
new_client (a_flow: attached like outflow)
local
new_connection: RG_CONNECTION
do
if max_to_poll <= a_flow.descriptor then
max_to_poll := a_flow.descriptor + 1
end
create new_connection.make (a_flow)
connections.extend (new_connection)
create message_out.make
message_out.extend ("Welcome! %N")
message_out.independent_store (a_flow)
poll.put_read_command (new_connection)
end
end
and the client:
class
RG_NETWORK_CLIENT
inherit
NETWORK_CLIENT
redefine
received
end
create
make_join
feature
make_join(ip:STRING)
require
is_ip_void : ip /= Void
local
l_client_name: detachable like client_name
do
check_name
l_client_name := client_name
make (1337, ip)
max_to_poll := in_out.descriptor + 1
create connection.make (in_out)
create poll.make_read_only
poll.put_read_command (connection)
send_name_to_server
auto_scan_server
processing
end
feature
connection: RG_CONNECTION
std_input: detachable RG_CONNECTION
message_out: RG_MESSAGE
received: detachable RG_MESSAGE
client_name: STRING
over: BOOLEAN
poll: MEDIUM_POLLER
input_poll: detachable MEDIUM_POLLER
max_to_poll: INTEGER
waiting:BOOLEAN
send_name_to_server
do
create message_out.make
message_out.set_client_name (client_name)
message_out.set_new (True)
message_out.set_over (False)
send (message_out)
end
processing
do
from
over := False
until
over
loop
scan_from_server
if not over then
read_content
end
end
cleanup
end
read_content
local
temp: detachable STRING
do
io.put_string ("Enter message: ")
io.readline
temp := io.laststring
if temp /= Void and not temp.is_empty then
if temp.is_equal ("bye") then
over := True
end
create message_out.make
message_out.extend (temp)
message_out.extend ("%N")
message_out.set_over (over)
message_out.set_client_name (client_name)
message_out.set_new (False)
send (message_out)
auto_scan_server
end
end
check_name
local
l_name: detachable STRING
do
io.putstring ("Enter your name : ")
io.readline
l_name := io.laststring
check
l_name_attached: l_name /= Void
end
client_name := l_name.twin
end
scan_from_server
local
l_received: like received
do
connection.initialize
poll.execute (max_to_poll, 1000)
if connection.is_waiting then
receive
l_received := received
if l_received /= Void then
waiting := FALSE
l_received.print_message
if l_received.over then
over := True
end
end
end
end
auto_scan_server
do
waiting := True
from until not waiting
loop
scan_from_server
end
end
end
The work around is the work with the samples provided from Eiffel, it works as longest the two persons are connected in the same network. for example as follow:
Here we define if the user has receive the message or is waiting for one, also redefine the poll_command to be able to use it.
inherit
POLL_COMMAND
redefine
make
end
create
make
feature {NONE} -- Initialization
make (s: IO_MEDIUM)
do
Precursor (s)
create client_name.make_empty
end
feature
is_waiting: BOOLEAN
client_name: STRING
execute (arg: ANY)
do
is_waiting := True
end
initialize
do
is_waiting := False
end
set_client_name (s: STRING)
require
s_exists: s /= Void
do
client_name := s.twin
end
end
Then following the chat sample, that can be found in the samples folder, in the message handler, we create the follow:
set_client_name (s: STRING)
require
s_not_void: s /= Void
do
client_name := s.twin
end
set_new (flag: BOOLEAN)
do
new := flag
end
Later in the connection class we are able to connect to a server ip, which it can be pass true command line or via GUI input.
make_join (name: STRING; ip: STRING; gc: RG_CLIENT)
require
is_ip_void: ip /= Void
do
-- Connects to IP on port 1337
make (1337, ip)
max_to_poll := in_out.descriptor + 1
create connection.make (in_out)
create poll.make_read_only
poll.put_read_command (connection)
-- Sets client name and refrence
client_name := name
p_client := gc
-- Sends name to server and receives ID
client_id := send_name_to_server
-- Launches instance as thread
make_thread
launch
execute
end
Then in the server class...
make_server (gs: RG_SERVER)
local
l_message_out: detachable like message_out
l_connections: detachable like connections
l_in: detachable like in
do
-- Instantiate reference and create server listening on port 1337
game_server := gs
make (1337)
max_to_poll := 1
create poll.make_read_only
in.set_non_blocking
l_in := in
create l_connections.make
connections := l_connections
connections.compare_objects
-- Launches instance as tread
make_thread
launch
end
There is a bit more code, but this is a good sample in how to do it, there must be a method to handle the connections, but this is a good start, also remember that all this is based on their samples, chat sample is a good point of start..
enjoy eiffel while is not crashing .

Parallel To Serial HDL

I am making a parallel to serial converter using ring counter in verilog. The ring counter is working fine but the Parallel to serial converter is not working properly and I am getting x undefined result. I am providing the code kindly help me finding the problem.
TOP
module PtoSTOP;
reg clk,rst;
wire [3:0] myout;
wire out;
Ring a(clk,rst,myout);
parToser x(myout,clk,rst,out);
initial begin
clk=1;
rst=1;
#1 rst=0;
end
always
#2 clk=~clk;
endmodule
Parallel TO Serial Converter
module parToser(myout,clk,rst,out);
input clk,rst;
input [3:0] myout;
output reg out;
reg [2:0]i;
always #(posedge clk or posedge rst) begin
if(rst) begin
out <= 0;
i <= 0;
end
else begin
out <= myout[i];
i <= i+1;
end
end
endmodule
RingCounter
module Ring(clk,rst,myout);
input clk,rst;
output reg [3:0]myout;
always #(posedge clk or posedge rst) begin
if(rst)
myout<=1;
else
myout<=myout<<1;
end
endmodule
I think the main issue you are seeing is part of parToser.
You have reg [2:0]i; which you increment and use to address input [3:0] myout; but i can hold values 0 to 7, half of which is outside the address range of [3:0] myout. You should be seeing a simulation error about out of range addressing.
Also you have included a few flip-flops with a reset condition but not added the reset to the sensitivity list in 'parToser' & 'Ring':
always #(posedge clk)
Should be:
always #(posedge clk or posedge rst)
With out this trigger your out, i and myout variables will be x, as they have not been set to a known condition.
NB: parToser i = i+1; should be i <= i+1;