Okay, i get it how transfer is differentiated in "Isolated I/O" by having different control lines for I/O and memory transfer. But how can we differentiate the transfer in Memory mapped I/O they share the same control lines. and also tell which type of bus architecture do modern systems use ( like today's core i3 or like that processors ) ???
Thanks
You can call different numbers on your land-line phone, yet the "control lines" are the same for every number.
You can send packet to different computers through your NIC, yet the "control lines" are the same for every packet.
You can drive from your home to different destinations, yet the "control lines" are the same for every destination.
In a word: routing.
For MMIO is the same, the address dictates which route the write will take.
I listed the typical connections used by a modern x86 CPU in this other answer of mine.
Related
Some CPU like x86 processor has two address spaces. One for memory and one for IO. And different instructions to access them.
And the PCI 3.0 spec also mentions some important IO addresses:
Two DWORD I/O locations are used to generate configuration
transactions for PC-AT compatible systems. The first DWORD location
(CF8h) references a read/write register that is named CONFIG_ADDRESS.
The second DWORD address (CFCh) references a read/write register named
CONFIG_DATA.
So it seems PCI 3.0 spec is tightly coupled to processors that does implement IO address space. And that's the a priori knowledge that SW/FW writers should know.
So what about the other processor archs that don't have IO address space? Like ARM. How can they interact with the PCI configuration space?
The paragraph immediately preceding the one quoted in the question directly addresses the question. It says:
Systems must provide a mechanism that allows software to generate PCI configuration transactions. ...
For PC-AT compatible systems, the mechanism for generating configuration transactions is defined and specified in this section. ...
For other system architectures, the method of generating configuration
transactions is not defined in this specification.
In other words, systems that are not PC-AT compatible must provide a mechanism, but it is specified elsewhere. The PCI spec isn't tightly coupled to PC-AT systems, but it doesn't define the mechanism for other types of systems.
The paragraph in the question only applies to PC-AT compatible systems.
Below quote from here clears things up:
The method for generating configuration cycles is host dependent. In
IA machines, special I/O ports are used. On other platforms, the PCI
configuration space can be memory-mapped to certain address locations
corresponding to the PCI host bridge in the host address domain.
And
I/O space can be accessed differently on different platforms.
Processors with special I/O instructions, like the Intel processor
family, access the I/O space with in and out instructions. Machines
without special I/O instructions will map to the address locations
corresponding to the PCI host bridge in the host address domain. When
the processor accesses the memory-mapped addresses, an I/O request
will be sent to the PCI host bridge, which then translates the
addresses into I/O cycles and puts them on the PCI bus.
So for non-IA platform, MMIO can just be used instead. And the platform specs should document that memory-mapped address for the PCI host bridge as the a priori knowledge for SW/FW writers.
ADD 1 - 14:36 2023/2/5
From the digital design's perspective, the host CPU and the PCIe subsystem are just two separate IP blocks. And the communication between them is achieved by a bunch of digital signals in the form of address/data/control lines. As long as the signals can be conveyed, the communication can be made.
For x86 CPUs, the memory address space and IO address space are just different usage of address lines down to the earth. I don't think there's any strong reason that memory addresses cannot be used to communicate with PCIe subsystem. I think it's a more logical choice back then to use I/O addresses for PCIe because PCIe is deemed as I/O.
So the real critical thing I think, is to convey the digital signals in proper format between IPs. PCIe is independent of CPU architectures and cares nothing about what lines to be used. For ARM, there's nothing unnatural to use memory addresses, i.e., MMIO. After all it's digital signals and are capable of passing necessary information properly.
An operating system/computer architecture question here. I was reading about caches, about how virtually indexing the cache is an option to reduce address translation time. I came across the following:
"Virtual cache difficulties include:
Aliasing
Two different virtual addresses may have the same physical address."
I can't think of a scenario when this can occur. It's been a while since my O/S days and I'm drawing a blank.
Could someone provide an example? Thanks
Two processes might have a shared mapping. E.g., in Unix, executable code is typically mapped into a region shared between all processes that execute the same program. (In fact, a single process might have several mappings of the same underlying memory, e.g. when it mmap's the same file twice.)
I believe that the executable sections of programs can possibly be shared between processes--thus being mapped twice.
For example: if you load two instances of vim, there will be two processes. Both process will likely map to the same executable code in physical memory.
shmat() is a typical example of same physical address being mapped as two different virtual address in two different processes.
If you do pmap -x pid_A .
you will you see the virtual mem map for process A similarly for Process B.
Actual Phy mem is not exposed to the user-space program.
Now SayProcess A and B share a shared memory segment and shared memory pointer be sh_mem_ptr_A and Sh_mem_ptr_B.
If you print these pointers their address(virtual) will be different.
Because Sh_mem_ptr_A is a part of memory map of Process A, Similarly sh_mem_ptr_B for Process B.
Kernel maintains the maaping of Virtual-to- phy addr. By page table and offset.
Higher bits map to the page table and offset maps to offset in the page table. So If you notice the Lower order bits of sh_mem_ptr_A and sh_mem_ptr_B they will be same(but may not be true always).
Also each process is allocated 4GB of virtual space (in 32 bit system), out of which 1 GB (depends upon Os to Os) is mapped for OS. Since OS is common for all processes, so the lower 1GB of virtual addresses are common for all the process, which are mapped to same OS physical pages.
I've read about the difference between port mapped IO and memory mapped IO, but I can't figure out how memory mapped Io is implemented in modern operating systems (windows or linux)
What I know is that a part of the physical memory is reserved to communicate with the hardware and there's a MMIO Unit involved in taking care of the bus communication and other memory-related stuff
How would a driver communicate with underlying hardware? What are the functions that the driver would use? Are the addresses to communicate with a video card fixed or is there some kind of "agreement" before using them?
I'm still rather confused
The following statement in your question is wrong:
What I know is that a part of the physical memory is reserved to communicate with the hardware
A part of the physical memory is not reserved for communication with the hardware. A part of the physical address space, to which the physical memory and memory mapped IO are mapped, is. This memory layout is permanent, but user programs do not see it directly - instead, they run into their own virtual address space to which the kernel can decide to map, wherever it wants, physical memory and IO ranges.
You may want to read the following articles which I believe contain answers to most of your questions:
http://duartes.org/gustavo/blog/post/motherboard-chipsets-memory-map
http://duartes.org/gustavo/blog/post/memory-translation-and-segmentation
http://duartes.org/gustavo/blog/post/how-the-kernel-manages-your-memory
http://en.wikipedia.org/wiki/Memory-mapped_I/O
http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/IO/mapped.html
Essentially it is just a form of accessing the data, as if you are saving / reading from the memory. But the hardware will snoop on the address bus, and when it sees the address targetting for him, it will just receive the data on the data bus.
Are you asking about Memory mapped files, or memory mapped port-IO?
Memory mapped files are done by paging out the pages and intercepting page-faults to those addresses. This is all done by the OS by negotiation between the file-system manager and the page-fault handler.
Memory mapped port-IO is done at the CPU level by overloading address lines as port-IO lines which allow writes to memory to be translated onto the QPI bus lines as port-IO. This is all done by the processor interacting with the motherboard. The only other thing that the OS needs to do is to tell the MMU not to coalese reads and writes through the PAE must-writethrough and no-cache bits.
Can someone very briefly point out the differences between the memory bus and address bus in computer architectures ? Also when you say memory bus does it imply that you are referring to the databus ?
Beautifully explained here.
In isolation, the microprocessor, the memory and the input/output
ports are interesting components, but they cannot do anything useful.
In combination, they can form a complete system if they can
communicate with each other. This communication is accomplished over
bundles of signal wires (known as buses) that connect the parts of the
system together.
There are normally three types of bus in any processor system:
An address bus: this determines the location in memory that the processor will read data from or write data to.
A data bus: this contains the contents that have been read from the memory location or are to be written into the memory location.
A control bus: this manages the information flow between components indicating whether the operation is a read or a write
and ensuring that the operation happens at the right time.
Data bus:
The data bus is an electrical path that connects the cpu,memory and the other hardware devices on the motherboard. the number of wires in the data bus affects the speed at which data can travel between components.Since each wire can transfer one bit at a time therefore,an 8-wire or one byte at a time.
Address bus:
The reason that the address bus is important is that the number of lines in it tells the maximum number of memory addresses.8 bit data is enough to represent 2(8 in power)=256.
Memory bus consists of an address bus (used to specify memory address) and data bus (used to specify value to be written to it).
When you read data from memory or write data to memory you operate with 2 different items, the address and the data. Somehow they have to be transferred between the CPU and memory. You can have two buses to transfer them independently. Or you can have just one and use it for both, one thing at a time.
Address and data buses may have different widths, that is, they may carry different number of bits.
Yes, memory bus usually means data bus (that carries the memory data).
Data bus is a bi-directional bus for fetching and storing data where as an Address bus is a unidirectional bus used to specify the address.
Excellent narration here http://www.differencebetween.com/difference-between-address-bus-and-vs-data-bus/
Pls explain the difference between memory mapped IO and IO mapped IO
Uhm,... unless I misunderstood, you're talking about two completely different things. I'll give you two very short explanations so you can google up what you need to now.
Memory-mapped I/O means mapping I/O hardware devices' memory into the main memory map. That is, there will be addresses in the computer's memory that won't actually correspond to your RAM, but to internal registers and memory of peripheral devices. This is the machine architecture Pointy was talking about.
There's also mapped I/O, which means taking (say) a file, and having the OS load portions of it in memory for faster access later on. In Unix, this can be accomplished through mmap().
I hope this helped.
On x86 there are two different address spaces, one for memory, and another one for I/O ports.
The port address space is limited to 65536 ports, and is accessed using the IN/OUT instructions.
As an example, a video card's VGA functionality can be accessed using some I/O ports, but the framebuffer is memory-mapped.
Other CPU architectures only have one address space. In those architectures, all devices are memory-mapped.
Memory mapped I/O is mapped into the same address space as program memory and/or user memory, and is accessed in the same way.
Port mapped I/O uses a separate, dedicated address space and is accessed via a dedicated set of microprocessor instructions.
As 16-bit processors will slowly become obsolete and replaced with 32-bit and 64-bit in general use, reserving ranges of memory address space for I/O is less of a problem, as the memory address space of the processor is usually much larger than the required space for all memory and I/O devices in a system.
Therefore, it has become more frequently practical to take advantage of the benefits of memory-mapped I/O.
The disadvantage to this method is that the entire address bus must be fully decoded for every device. For example, a machine with a 32-bit address bus would require logic gates to resolve the state of all 32 address lines to properly decode the specific address of any device. This increases the cost of adding hardware to the machine.
The advantage of IO Mapped IO system is that less logic is needed to decode a discrete address and therefore less cost to add hardware devices to a machine. However more instructions could be needed.
Ref:- Check This link
I have one more clear difference between the two. The memory mapped I/O device is that I/O device which respond when IO/M is low. While a I/O (or peripheral) mapped I/O device is that which respond when IO/M is high.
Memory mapped I/O is mapped into the same address space as program memory and/or user memory, and is accessed in the same way.
I/O mapped I/O uses a separate, dedicated address space and is accessed via a dedicated set of microprocessor instructions.
The difference between the two schemes occurs within the Micro processor’s / Micro controller’s. Intel has, for the most part, used the I/O mapped scheme for their microprocessors and Motorola has used the memory mapped scheme.
https://techdhaba.com/2018/06/16/memory-mapped-i-o-vs-i-o-mapped-i-o/