I am trying to compile the following SystemVerilog, and I get the following error "Error (10686): SystemVerilog error at InstRom.sv(8): InstAddress has an aggregate value."
module InstRom#(parameter A = 16, parameter W = 9)
(
input InstAddress[A-1:0],
output logic InstOut[W-1:0]
);
logic[W-1:0] instr_rom[2**(A)];
always_comb InstOut = instr_rom[InstAddress];
initial begin
$readmemb("cordic.txt", instr_rom);
end
endmodule
What am I doing wrong?
InstAddress is an unpacked array of bit, not a bit vector (i.e. a packed array). The same applies to InstOut. Change the declaration to
input logic [A-1:0] InstAddress,
output logic [W-1:0] InstOut
and your code should work.
Related
I have a .txt file that contains certain signals that I want to monitor in my testbench during the application of some stimulus.
I am creating an initial block in which I am reading the file and then I try to generate a init_signal_spy() for every one of the lines that I have read.
The code that I have written up until this point has the following format:
module testbench();
logic probes[];
initial begin : read_signals_to_dump_at
automatic int fd;
automatic string fname,line,line_stripped;
if ($value$plusargs("sigfile=%s",fname)) begin : read
fd = $fopen(fname,"r");
while($fgets(line,fd)) begin
//static logic net_to_be_probed;
automatic sig_and_spy entry = new();
// Trim away the '\n' from the line.
line_stripped = line.substr(0,line.len()-2);
// Resize the array
probes = new [probes.size() + 1] (probes);
// Link the extracted new line with the probe list
// - this raises an error "An invalid empty string was passed in as the Destination object."
// - expected since the last element is empty...
$init_signal_spy(line_stripped, probes[probes.size()-1] , 1);
end
end
end : read_signals_to_dump_at
endmodule
In the code above, just before I issue the generation for the spy, I get why the error
An invalid empty string was passed in as the Destination object.
is generated by the compiler. Although the array has been resized, it does not hold any element i.e., its empty. Thus, I tried creating locally a logic variable that then I assign to the signal spy within the loop in the following manner:
module testbench();
logic probes[];
initial begin : read_signals_to_dump_at
automatic int fd;
automatic string fname,line,line_stripped;
if ($value$plusargs("sigfile=%s",fname)) begin : read
fd = $fopen(fname,"r");
while($fgets(line,fd)) begin
logic new_probe;
// Trim away the '\n' from the line.
line_stripped = line.substr(0,line.len()-2);
// Resize the array and copy old values.
probes = new [probes.size() + 1] (probes);
// Add the new probe to the Testbenchs' probes array
probes[probes.size()-1] = new_probe;
// Again, An invalid empty string was passed in as the Destination object.
$init_signal_spy(line_stripped, probes[probes.size()-1] , 1);
end
end
end : read_signals_to_dump_at
endmodule
But then again, I see the same error at runtime during the simulation. So...Is there a way of achieving such a "dynamic" signal monitoring in the testbench somehow? As far as I understood the error concerns that the destination object is NOT a signal of the testbench. Thus the logic new_probe has no effect. Which is to be expected I mean, but is there a way of achieving the desired behavior in the Testbench via sysverilog?
You have at least two problems.
Both the source and destination arguments to init_signal_spy() need to be strings. Your destination argument is an integral variable with a 0 value, and that gets interpreted as a null string. init_signal_spy() was designed for mixed language simulation, and using strings was the only way to achieve that.
Your destination variable should be queue, not a dynamic array. Every time you re-size a dynamic array, the previous elements get relocated and that breaks the previous connection made by signal spy.
This example shows the proper syntax for string this up
module top;
int A[$];
int s1,s2;
initial begin
A.push_back(0);
$init_signal_spy("s1","A[0]");
A.push_back(0);
$init_signal_spy("s2","A[1]");
#1 s1 = 1;
#1 s2 = 2;
#1 $display("%p",A);
end
endmodule
A far better solution for performance is converting your .txt file into actual SystemVerilog code that can be compiled into your testbench.
module rev_array;
int array_in[10]={0,1,2,3,4,5,6,7,8,9};
typedef integer array[9:0];
function array reverse(int array_in[10]);
for(int j=$size(array_in)-1,int i=0;j>=0;j--,i++)
begin
reverse[j]=array_in[i];
end
// working for(integer k=0;k<$size(array_in)-1;k++)
// working $display("reverse[%0d]:%0d", k, reverse[k]);
$display("inside function");
endfunction:reverse
initial
begin
reverse(array_in);
for(integer k=0;k<$size(array_in)-1;k++)
begin
$display("reverse[%0d]:%0d", k, reverse[k]);
end
end
endmodule
Error-[IUS] Illegal use of scope
testbench.sv, 22
rev_array, "rev_array.reverse"
Scope cannot be used in this context
Error-[XMRIBS] Illegal bit select
testbench.sv, 22
Error is found in following cross-module reference, illegal bit select on
the target.
Source info: $display("reverse[%0d]:%0d", k, rev_array.reverse[k]);
I am trying to reverse an array and return it in system verilog function, I am able to see the reversed array inside the function by printing it but
when I try to print it using $display outside the function, I think it is
not being returned properly somehow, in the 4th line from end, getting
errorError-[IUS]
your both issues are related to the line where you use reverse function name as an array within $display.
$display("reverse[%0d]:%0d", k, reverse[k]);
--------------------------------^^^^^^^^^^
this is an illegal syntax causing both messages.
your initial block should look like the following.
initial
begin
array result;
result = reverse(array_in);
//^^^^^^^^^^^^^^^^^^^^^^^^^//
for(integer k=0;k<$size(array_in)-1;k++)
begin
$display("reverse[%0d]:%0d", k, result[k]);
// ^^^^^^ //
end
end
call the function and use returned results for display.
module rev_array;
initial
begin
int array_in[10]={0,1,2,3,4,5,6,7,8,9};
typedef integer array[9:0];
function array reverse(int array_in[10]);
array reverse;
for(integer i=0;i<$size(array_in)-1;i++)
begin
for(int j=$size(array_in)-1;j>=0;j--)
begin
reverse[j]=array_in[i];
end
end
return reverse;
endfunction:reverse
reverse(array_in);
for(integer k=0;k<$size(array_in)-1;k++)
begin
$display("reverse[%0d]:%0d", k, reverse[k]);
end
end
endmodule
For the above code, I am getting error
Error-[SE] Syntax error
Following verilog source has syntax error :
"testbench.sv", 7: token is 'function'
function array reverse(int array_in[10]);
I want to return an array named reverse(same name as the function ) which has 10 elements, each element being an integer, what am I doing wrong here ?
You cannot define a function in the middle of a procedural block. Move it to the top level of the module. You have many other problems. Note there is a built-in reverse array method.
While updating Modelsim from 10.3c to 10.6a, I encountered an error on this piece of code that used to not work without warning:
module test(
input bit clk,
input bit signed[31:0] data
);
real rdata_dl[19:0] = '{20{0}};
real rdata = 0;
always #(posedge clk) begin
rdata_dl = {rdata_dl[18:0], rdata};
rdata = data;
end
endmodule
-- Compiling module test
** Note: test.sv(10): (vlog-13177) Promoting concatenation '{rdata_dl[18:0],rdata}' to an assignment pattern: Assigning to a real/wreal array.
** Error (suppressible): (vlog-13215) test.sv(10): Assignment pattern element 'rdata_dl[18:0]': Cannot assign an unpacked type 'real $[18:0]' to a packed type 'real'.
** Error (suppressible): test.sv(10): (vlog-13174) Illegal assignment pattern. The number of elements (2) doesn't match with the type's width (20).
I managed to fix it by using this line instead: rdata_dl = {rdata_dl[18:0], real'(rdata)};.
However, I fail to understand why it failed and why the new version would work. Can anyone explain?
not sure what you are trying to do with this code. real type is 64-bit. When concatenating it with 19-bits, you're getting a 83-bit bus, where the rdata is in the LSBs.
Now, when assigning this 83-bit vector to a 20-bit bus, it will take the 20 LSBs, meaning that it is equivalent to writing the following assignment:
always #(posedge clk) begin
rdata_dl = rdata[19:0];
rdata = data;
end
I am using openmodelica and I am trying to loop through an array in order to find the maximum value. I was able to reduce my code to a very simple test case that still gives the error. Is this something that I am doing wrong, or is this a bug in openmodelica? Here is a very simple case that does give the error:
package TestLoop
model ItemA
Real p;
end ItemA;
model ItemB
ItemA a[n];
parameter Integer n = 5;
Real p;
equation
for i in 1:n loop
a[i].p = time;
end for;
algorithm
for i in 1:n loop
p := a[i].p;
end for;
end ItemB;
end TestLoop;
The problem is in my algorithm section. Here is the error that I am getting:
TestLoop.ItemB.c:155:13: warning: implicit declaration of function '$Pa$lB' is invalid in C99 [-Wimplicit-function-declaration]
$Pp = $Pa$lB(modelica_integer)$Pi$rB$Pp;
^
TestLoop.ItemB.c:155:20: error: unexpected type name 'modelica_integer': expected expression
$Pp = $Pa$lB(modelica_integer)$Pi$rB$Pp;
^
1 warning and 1 error generated.
Any suggestions for why this might be, or how I can work around it? If I replace the assignment with a fixed value, p:=a[1].p;, the code does run (although that is not useful to me). What I ultimately want to do in the algorithm section is find the largest value of a[n].p, where I do have an equation section that does useful calculations into the array of items.
Yes, the code generation is an error of OpenModelica (it does not like unknown array indexes). Your problem is very easy to solve in a single line though (one of the following):
p = max(r for r in a.p);
p = max(a.p);