I have a non ethernet phy interfaced on the MDIO bus of NXP MPC8308 controller. I want to access the phy registers from u-boot using 'mii' command, as of now the 'mii info' is not listing this device which has address '6' in the MDIO bus.
In the case of Ethernet PHY I would go to drivers/net/tsec.c and add the structure info in 'struct phy_info *phy_info[]' for the probe function to detect it.
A phy in question is CFP module which follows MDIO interface definition in IEEE 802.3 Clause 45, http://www.cfp-msa.org/Documents/CFP_MSA_MIS_V2p2r06a.pdf
Any help is appreciated.
Greg
Related
I am trying to use the rpi pico as a I2C slave capable of receiving and sending multiples bytes using interrupts.
Using the rpi pico as a I2C slave/memory with micropython is possible. (https://forums.raspberrypi.com/viewtopic.php?t=302978).
I am now trying to implement reading from the pico using interrupt.
According to the pico documentation, when the master tries to read data from the pico, the RD_REQ is set to 1. Then the pico hold the scl to 1 until and IRQ handler write data in the IC_DATA_CMD register and disable the interrupt. (https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#page=481)
In the documentation the interrupts sources are defined as I2C0_IRQ or I2C1_IRQ (https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#page=60)
So far, I only found how to create interrupt handle linked to specific pin. I do not understand how to link the callback function to the interrupt source or the RD_REQ bit.
I'm using PySerial to communicate to some devices over RS485 multi-drop. I am bit-banging the DE signal to enable transmission before sending a packet and releasing it at the end.
The problem is that the time for release varies, especially under processor load, and the responses from the devices get clobbered (and aren't received).
I know PySerial has RS485 support, but from everything I've read about my embedded SBC (NXP iMX6 Dual), the RTS signal is not available on the GPIO connector. I just have arbitrary GPIO to use.
Is there a way to map an arbitrary GPIO signal to the RTS functionality so that the Linux tty drivers will assert/deassert my desired GPIO pin?
The following statement gives me some hope (https://www.kernel.org/doc/html/v4.17/driver-api/gpio/drivers-on-gpio.html)
"""
... there are special GPIO drivers in subsystems like ... the TTY serial subsystem to emulate MCTRL (modem control) signals CTS/RTS by using two GPIO lines.
"""
There seems to be some kind of support for in the tty driver for /dev/ttyimxN devices.
https://github.com/torvalds/linux/blob/v4.14/drivers/tty/serial/serial_mctrl_gpio.h
https://github.com/torvalds/linux/blob/v4.14/drivers/tty/serial/imx.c
unsigned int have_rtsgpio:1;
But how can I set this up with PySerial?
How can I specify the GPIO port to use (if at all)?
Thanks for any help !!
EDIT
I've found info in the kernel sources that match the kernel on my board. This describes how to specify the gpio for modem control emulation (software control, instead of hardware control).
https://github.com/ADVANTECH-Corp/linux-imx/blob/adv_4.14.98_2.0.0_ga/Documentation/devicetree/bindings/serial/serial.txt
So it seems possible by changing the device tree sources and making a new device tree blob for my system.
This should all be independent of pyserial.
I'm not sure if this can be set/overridden at runtime with an ioctl, which would be handy (instead of having to muck around with kernel sources and building device tree blobs, etc).
describe how a JTAG connection is used to test the circuitry in a chip using just 5 pins
JTAG is used as a synonyme for the boundary scan protocol, see
- https://en.wikipedia.org/wiki/JTAG#Boundary_scan_testing
- https://en.wikipedia.org/wiki/Boundary_scan
It was the Joint Test Action Group (JTAG) who originally devised this protocol for testing circuitry around chips.
Besides this original purpose, the same protocol is used to program and debug CPUs, FPGAs etc.
In order to use JTAG, you need an adapter device that supports the circuitry you would like to test/debug.
[...] using just 5 pins
You are wondering how to test the entire chip through "just" 5 pins? To get a rough idea, think of a shift register similar to UART and SPI (but keep in mind that JTAG is notably more sophisticated).
Does the bpf helper function bpf_skb_get_xfrm_state() suppose to work
for ipsec using transport mode or only for tunnel mode?
Is there any possibility with bpf to create new SA/SP (transport mode)
on the fly when an ESP packet is received but there is no SA/SP
present for the corresponding SPI, provided that all necessary
information for the creation is available in the bpf program?
I tried to find an answer to this question by searching SDIO which is related to my question based on Silicon Labs naming of data channels. However, I was flooded with topics related to the SDIO protocol for serial comms with an SD memory card - a totally different concern.
I want to interface a PIC MCU (SPI bus) with Silicon Labs FM TX/RX 47XX chips which describe a serial control interface and the multiple ways to use it - what they call 2-wire (basically I2C) or what they call 3-wire and refer to as "SPI". The 3 lines are SLCK, SEN and SDIO (clock, enable, and data input/output half-duplex over the same wire).
My problem is that SPI is full duplex capable - TX and RX simultaneously. Even though every implementation I've seen of this is really half-duplex - send then receive - the hardware is wired with SDI/SDO or MISO/MOSI or called whatever lines in the SPI module; a separate data IN and a data OUT wire. Along with SCLK and SEN (clock and enable).
I'm not sure how to wire this up - and whether it will work. Do I wire both the SDI and SDO pins of the PIC (SPI module) to the same SDIO on the Si47XX? Since the Si47XX is half-duplex that would make sense; but I've never seen the two lines tied on an SPI interface. Not sure if the pins are always Hi-Z for example and I don't want to fry something out. Would I need to add pull ups/downs?
Oddly, I can't seem to find an actual wiring diagram of such a case. When I search 3-wire SPI I always get examples where SEN is tied since only one slave device is being used - not my situation. Any advice would be - as always - greatly appreciated.
-Rick
One can interconnect SPI and 3-wire devices using the following schematic. It does not matter which device is master and which is slave.
SPI device 3-wire device
----+
SDO |--/\/\/\-+ 3k
| | +---
SDI |---------*--------| SDIO
| |
SCK |------------------| SCK
SEN |------------------| SEN
----+ +---
If a 3-wire device is in reception state, then SDO signal comes via resistor to (Hi-Z) SDIO pin and back to SDI pin.
If the 3-wire device is in transmission state, then SDIO output overrides SDO value.
The example of such connection one can see in FTDI datasheet for FT2232H, page 37 (Figure 4.1RS232 Configuration) — 93С46 to FT2232H connection.
At lower SPI frequencies one can use higher resistor value for lower overriding current. It's depend also from traces length but in usual cases 3k is in very good marging for frequences up to 2 MHz.
p.s. It seems that the question is not about programming. Could it be moved to electronics.stackexchange.com?