"consecutive SC failures" on gem5 simple config script - cpu-architecture

Question

I am new to gem5 and I ran into a problem while trying to write a simple multi-core system configuration script. my script is based on the example scripts given on: http://learning.gem5.org/book/part1/cache_config.html
When i try to add more than one dcache to the system (for each different core) im getting an infinite loop of this warning message:
warn: 186707000: context 0: 10000 consecutive SC failures.
incremented by 10000 each time.
I tried looking in gem5's given configuration scripts se.py and CacheConfig.py but I still cant understand what im missing here. I know that I can just simulate this configuration using se.py but I tried to do this by myself as practice and to get a deeper understanding of the gem5 simulator.
some additional info: im running gem5 in se mode and trying to simulate a simple multicore system using riscv cores.
this is my code:
import m5
from m5.objects import *
from Caches import *
#system config
system = System(cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(4)])
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]
system.cpu_voltage_domain = VoltageDomain()
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',voltage_domain= system.cpu_voltage_domain)
system.membus = SystemXBar()
system.l2bus = L2XBar()
multiprocess =[Process(cmd = 'tests/test-progs/hello/bin/riscv/linux/hello', pid = 100 + i) for i in xrange(4)]
#cpu config
for i in xrange(4):
system.cpu[i].icache = L1ICache()
system.cpu[i].dcache = L1DCache()
system.cpu[i].icache_port = system.cpu[i].icache.cpu_side
system.cpu[i].dcache_port = system.cpu[i].dcache.cpu_side
system.cpu[i].icache.mem_side = system.l2bus.slave
system.cpu[i].dcache.mem_side = system.l2bus.slave
system.cpu[i].createInterruptController()
system.cpu[i].workload = multiprocess[i]
system.cpu[i].createThreads()
system.l2cache = L2Cache()
system.l2cache.cpu_side = system.l2bus.master
system.l2cache.mem_side = system.membus.slave
system.system_port = system.membus.slave
system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
root = Root(full_system = False , system = system)
m5.instantiate()
print ("Begining Simulation!")
exit_event = m5.simulate()
print ('Exiting # tick {} because {}' .format(m5.curTick() , exit_event.getCause()))