Why DTBO fails on load and says no symbols in root of device tree.? - linux-device-driver

Question

I am trying to build a DTBO from a dts file.
I have a few questions here.
I get a warning when I build this -
/opt/poky/2.7.3/sysroots/x86_64-pokysdk-linux/usr/bin/dtc -o dtb -o phyDriver.dtbo -# ./phyDriver.dts
(avoid_unnecessary_addr_size): /fragment#1/__overlay__: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Here is my phyDriver.dts file from which I have generated the dtbo file.
/dts-v1/;
/plugin/;
/ {
fragment#1 {
target = <&phy0>;
__overlay__ {
#address-cells = <0x1>;
#size-cells = <0x1>;
custom_port_phy {
#address-cells = <1>;
#size-cells = <0>;
compatible = "custom,custom-port-phy";
Dummy_Port_Phy0: dummy_port_phy#0 {
reg = <0>;
speed = <1000>;
};
Dummy_Port_Phy1: dummy_port_phy#1 {
reg = <1>;
speed = <1000>;
};
};
};
};
};
OF: resolver: no symbols in root of device tree.
OF: resolver: overlay phandle fixup failed: -22
create_overlay: Failed to create overlay (err=-22)
Here is my dts file. I am not sure what should be the target value. But, I think the problem is with the target. Here is my root dts file. I see that I have a phy0 entry in my root dts file. Is there anything
I can do to surpass this. My aim is to be able to insert this DTBO so that my phy driver works.
I don't care what target value is.
/dts-v1/;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
model = "Avnet MicroZed board";
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
cpu#0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
clocks = <0x1 0x3>;
clock-latency = <0x3e8>;
cpu0-supply = <0x2>;
operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
};
cpu#1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
clocks = <0x1 0x3>;
};
};
fpga-full {
compatible = "fpga-region";
fpga-mgr = <0x3>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
pmu#f8891000 {
compatible = "arm,cortex-a9-pmu";
interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
interrupt-parent = <0x4>;
reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
};
fixedregulator {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <0xf4240>;
regulator-max-microvolt = <0xf4240>;
regulator-boot-on;
regulator-always-on;
phandle = <0x2>;
};
amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x4>;
ranges;
adc#f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0x0 0x7 0x4>;
interrupt-parent = <0x4>;
clocks = <0x1 0xc>;
};
can#e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x1 0x13 0x1 0x24>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0x0 0x1c 0x4>;
interrupt-parent = <0x4>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can#e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <0x1 0x14 0x1 0x25>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0x0 0x33 0x4>;
interrupt-parent = <0x4>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio#e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <0x2>;
clocks = <0x1 0x2a>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x14 0x4>;
reg = <0xe000a000 0x1000>;
};
i2c#e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x1 0x26>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x19 0x4>;
reg = <0xe0004000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
i2c#e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <0x1 0x27>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x30 0x4>;
reg = <0xe0005000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
interrupt-controller#f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
phandle = <0x4>;
};
cache-controller#f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xf8f02000 0x1000>;
interrupts = <0x0 0x2 0x4>;
arm,data-latency = <0x3 0x2 0x2>;
arm,tag-latency = <0x2 0x2 0x2>;
cache-unified;
cache-level = <0x2>;
};
memory-controller#f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
ocmc#f800c000 {
compatible = "xlnx,zynq-ocmc-1.0";
interrupt-parent = <0x4>;
interrupts = <0x0 0x3 0x4>;
reg = <0xf800c000 0x1000>;
};
serial#e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <0x1 0x17 0x1 0x28>;
clock-names = "uart_clk", "pclk";
reg = <0xe0000000 0x1000>;
interrupts = <0x0 0x1b 0x4>;
};
serial#e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "okay";
clocks = <0x1 0x18 0x1 0x29>;
clock-names = "uart_clk", "pclk";
reg = <0xe0001000 0x1000>;
interrupts = <0x0 0x32 0x4>;
};
spi#e0006000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <0x4>;
interrupts = <0x0 0x1a 0x4>;
clocks = <0x1 0x19 0x1 0x22>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi#e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <0x4>;
interrupts = <0x0 0x31 0x4>;
clocks = <0x1 0x1a 0x1 0x23>;
clock-names = "ref_clk", "pclk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
spi#e000d000 {
clock-names = "ref_clk", "pclk";
clocks = <0x1 0xa 0x1 0x2b>;
compatible = "xlnx,zynq-qspi-1.0";
status = "disabled";
interrupt-parent = <0x4>;
interrupts = <0x0 0x13 0x4>;
reg = <0xe000d000 0x1000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
memory-controller#e000e000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "disabled";
clock-names = "memclk", "apb_pclk";
clocks = <0x1 0xb 0x1 0x2c>;
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
interrupt-parent = <0x4>;
interrupts = <0x0 0x12 0x4>;
ranges;
reg = <0xe000e000 0x1000>;
flash#e1000000 {
status = "disabled";
compatible = "arm,pl353-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
flash#e2000000 {
status = "disabled";
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
};
ethernet#e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-mode = "rgmii-id";
phy-handle = <0x5>;
ethernet-phy#0 {
reg = <0x0>;
phandle = <0x5>;
};
};
ethernet#e000c000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0x0 0x2d 0x4>;
clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
mmc#e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "okay";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x1 0x15 0x1 0x20>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x18 0x4>;
reg = <0xe0100000 0x1000>;
};
mmc#e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <0x1 0x16 0x1 0x21>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x2f 0x4>;
reg = <0xe0101000 0x1000>;
};
slcr#f8000000 {
u-boot,dm-pre-reloc;
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xf8000000 0x1000>;
ranges;
phandle = <0x6>;
clkc#100 {
u-boot,dm-pre-reloc;
#clock-cells = <0x1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
ps-clk-frequency = <0x1fca055>;
phandle = <0x1>;
};
rstc#200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <0x1>;
syscon = <0x6>;
};
pinctrl#700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <0x6>;
usb0-default {
phandle = <0x8>;
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <0x0>;
io-standard = <0x1>;
};
conf-rx {
pins = "MIO29", "MIO31", "MIO36";
bias-high-impedance;
};
conf-tx {
pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39";
bias-disable;
};
};
};
};
dmac#f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <0x4>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x4>;
clocks = <0x1 0x1b>;
clock-names = "apb_pclk";
};
devcfg#f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <0x4>;
interrupts = <0x0 0x8 0x4>;
reg = <0xf8007000 0x100>;
clocks = <0x1 0xc 0x1 0xf 0x1 0x10 0x1 0x11 0x1 0x12>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <0x6>;
phandle = <0x3>;
};
efuse#f800d000 {
compatible = "xlnx,zynq-efuse";
reg = <0xf800d000 0x20>;
};
timer#f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <0x1 0xb 0x301>;
interrupt-parent = <0x4>;
clocks = <0x1 0x4>;
};
timer#f8001000 {
interrupt-parent = <0x4>;
interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
compatible = "cdns,ttc";
clocks = <0x1 0x6>;
reg = <0xf8001000 0x1000>;
};
timer#f8002000 {
interrupt-parent = <0x4>;
interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
compatible = "cdns,ttc";
clocks = <0x1 0x6>;
reg = <0xf8002000 0x1000>;
};
timer#f8f00600 {
interrupt-parent = <0x4>;
interrupts = <0x1 0xd 0x301>;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clocks = <0x1 0x4>;
};
usb#e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "okay";
clocks = <0x1 0x1c>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x15 0x4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
dr_mode = "host";
usb-phy = <0x7>;
pinctrl-names = "default";
pinctrl-0 = <0x8>;
};
usb#e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <0x1 0x1d>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x2c 0x4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog#f8005000 {
clocks = <0x1 0x2d>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <0x4>;
interrupts = <0x0 0x9 0x1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <0xa>;
};
};
aliases {
ethernet0 = "/amba/ethernet#e000b000";
serial0 = "/amba/serial#e0001000";
};
memory#0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0x0>;
phandle = <0x7>;
};
};

Answer 1

Problem 1: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Your __overlay__ node has #address-cells and #size-cells, this means you should have a reg property in its subnodes (i.e. custom_port_phy) that set the address and size (or use the ranges property).
Since you need no addressing of subnodes, just remove #address-cells and #size-cells from __overlay__.
On the other hand, the #address-cells and #size-cells in the custom_port_phy are correct, because its subnodes (dummy_port_phy#0 and dummy_port_phy#1) do have a reg property.
The result should be:
/dts-v1/;
/plugin/;
/ {
fragment#1 {
target = <&phy0>;
__overlay__ {
// Remove these (custom_port_phy has no reg)
// #address-cells = <0x1>;
// #size-cells = <0x1>;
custom_port_phy {
// Leave these (dummy_port_phy#X have reg)
#address-cells = <1>;
#size-cells = <0>;
compatible = "custom,custom-port-phy";
Dummy_Port_Phy0: dummy_port_phy#0 {
reg = <0>;
speed = <1000>;
};
Dummy_Port_Phy1: dummy_port_phy#1 {
reg = <1>;
speed = <1000>;
};
};
};
};
};
Problem 2: no symbols in root of device tree
You need to compile the base device tree with the -# flag. This way the base tree will expose its __symbols__ (including the phy0 you need) and it will be found when applying the overlay.
See the kernel code that emits that error.