Virtual memory is something that can be indexed by CPU alone, a 32 bit architecture is capable of generating 2^32 locations(say byte addressable machine then 2^32 bytes=4GB).
Surely we can use demand paging if process size is bigger than RAM, but what if the process size is bigger than virtual memory itself ?
Surely, you can again use demand paging, but my question is, how can CPU locate any bytes greater than 2^32 ? Say program is written has size of 5GB, how does cpu index the bytes greater than 5GB ? It can only generate locations till 4GB.
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I am new to the concept of virtual memory.
I will like to know whats the maximum space of memory a procces can use through virtual memory?
Is it available RAM + available swap space ??
(This question has already been asked but people had different opinions on this issue)
For most systems the maximum size of virtual memory is determined by the number of bits in a virtual address that are supported by the MMU.
For example; for typical 64-bit 80x86 CPUs a virtual address is 64 bits, but only the lowest 48 bits are supported by the MMU, so the virtual address size is 1 << 48 = 256 TiB. Everything else (amount of RAM, swap space, etc) doesn't matter.
In theory, you can (e.g.) fill the entire virtual address space by mapping the same page of RAM everywhere; and (for 64-bit 80x86) it would only cost 4 KiB of RAM (for the data that's mapped everywhere) plus another 16 KiB of RAM (for MMU's own data - page tables, etc). In other words, a measly 20 KiB of physical RAM is enough to fill a whopping 256 TiB of virtual space.
Of course for practical purposes often the kernel reserves some of the virtual address space (e.g. half of it), so a process can only use the remainder (e.g. 128 TiB); and (for modern 64-bit CPUs) unless you're mapping the same data at different places in the virtual address space (which would be silly/pointless) it's likely that you'll run out of things to put in a virtual address space before you run out of virtual address space.
This isn't the case for older 32-bit CPUs, where the virtual address space is a lot smaller (where maybe a process can only use 2 GiB out of a 4 GiB total space) and it's a lot easier to run out of space.
a) Suppose there is a RAM of size 4GB installed in an intel Core i5 computer. If the system supports 64bit word then how many words can be stored in the RAM? Also how many bits will be required to address each Word uniquely?
There are a lot of variables to this question. How big are the words? How much RAM does Microsoft let Word use before it starts swapping data in a pagefile? Is any compression used?
If we assume that Word has access to all 4GB of RAM (the OS, and Word aren't using any in this situation), that there is no pagefile to dump to, and no compression going on in the background, we can do some simple math to find out. We know that typically a single ascii character takes up 1 byte of memory, and that there are 1024 bytes in a KB, 1024 KB in a MB, and so on. So, we just multiply until we get to 4GB worth of bytes. 1024 Bytes X 1024 KB X 1024 MB X 4 GB = 4,294,967,296 ascii characters.
Coincidentally, that's the maximum number of possible 32-bit addresses in 32bit systems, and why 32bit systems were unable to support more than 4GB of RAM without Physical Address Extension (PAE). With so little RAM, it doesn't matter that the program is 64bit, it just means it can handle addressing and integers larger than that if the RAM is available.
I hope that helps you in some way! I'm kind of concerned that you are having to worry about the maximum number of words that can be stored in 4GB.
Suppose we have a 64 bit processor with 8GB ram with frame size 1KB.
Now main memory size is 2^33 B
So number of frames is 2^33 / 2^10 which is 2^23 frames.
So we need 23 bits to uniquely identify every frame.
So the address split would be 23 | 10 where 10 bits are required to identify each byte in a frame (total 1024 bytes)
As it is word addressable with each word = 8B, will the address split now be 23 | 7 as we have 2^7 words in each frame?
Also can the data bus size be different than word size ?
If suppose data bus size is 128 bits then does it mean that we can address two words and transfer 2 words at a time in a single bus cycle but can only perform 64 bit operations?
Most of the answers are dependent on how the system is designed. Also there is bit more picture to your question.
There is something called available addressable space on a system. In a 32 bit application this would be 2^32 and in a 64 bit application this would be 2^64. This is called virtual memory. And there is physical memory which commonly refereed as RAM. If the application is built as 64 bits, then it is able work as if there is 2^64 memory is available. The underlying hardware may not have 2^64 RAM available, which taken care by the memory management unit. Basically it breaks both virtual memory and physical memory into pages( you have refereed to this as frames) and keeps the most frequently used pages in RAM. Rest are stored in the hard disk.
Now you state, the RAM is 8GB which supports 2^33 addressable locations. When you say the processor is 64 bits, I presume you are talking about a 64 bit system which supports 2^64 addressable locations. Now remember the applications is free to access any of these 2^64 locations. Number of pages available are 2^64/2^10 = 2^54. Now we need to know which virtual page is mapped to which physical page. There is a table called page table which has this information. So we take the first 54 bits of the address and index in to this table which will return the physical page number which will be 2^33/2^10 = 23 bits. We combine this 23 bits to the least 10 bits of the virtual address which gives us the physical address. In a general CPU, once the address is calculated, we don't just go an fetch it. First we check if its available in the cache, all the way down the hierarchy. If its not available a fetch request will be issued. When a cache issues a fetch request to main memory, it fetches an entire cache line (which is usually a few words)
I'm not sure what you mean by the following question.
As it is word addressable with each word = 8B, will the address split now be 23 | 7 as we have 2^7 words in each frame?
Memories are typically designed to be byte addressable. Therefore you'll need all the 33 bits to locate a byte within the page.
Also can the data bus size be different than word size ?
Yes you can design a data bus to have any width, but having it less than a byte would be painful.
If suppose data bus size is 128 bits then does it mean that we can
address two words and transfer 2 words at a time in a single bus cycle
but can only perform 64 bit operations?
Again the question is bit unclear, if the data but is 128 bits wide, and your cache line is wider than 128 bits, it'll take multiple cycles to return data as a response to a cache miss. You wont be doing operations on partial data in the cache (at least to the best of my knowledge), so you'll wait until the entire cache line is returned. And once its there, there is no restriction of what operations you can do on that line.
For a 2GBytes memory, suppose its memory width is 8 bits….
what is the address space of the memory?
what is the address width of the memory?
I’m not looking for the answer to question, I’m just trying to understand the process of how to get there.
EDIT: all instances of Gb replaced with GB
The address-space is the same as the memory size. This was not true (for example) in 32 bit operating systems that had more than 2^32 bytes of memory installed. Since the number of bits used for addressing is not specified in your question, one can only assume it to be sufficient to address the installed memory. To contrast, while you could install more than 4GB in a 32 bit system, you couldn't access more than 4GB, since (2^32)-1 is the location of the last byte you could access. Bear in mind, this address-space must include video memory and any/all bioses in the system. This meant that in 32bit WinXP MS limited the amount of user-accessible memory to a figure considerably less than 4GB.
Since the memory width is 8 bits, each address will point to 1 byte. Since you've got 2GB, you need to use a number of bits for addressing that is equal-to or greater-than that which will allow you to point to any one of those bytes.
Spoiler:
Your address-space is 2GB and you need 31 bit wide addresses to use it all.
I am very much confused about the allocation of virtual memory to a process.
How does the OS determine the amount of "virtual memory" which should be assigned to a process? Does it depend on the process size?
Does it depend on the size of the RAM ("main memory")? If yes, then suppose the size of the RAM is 4GB, and the resident OS takes 1GB for its execution: how much virtual memory will be assigned to a process?
The virtual memory is usually the sum of the resident memory and everything that is not mapped into physical memory, e.g. swap, open files etc. The operating system doesn't determine the size of the memory -- a process allocates memory explicitly to do what it wants to do. Other memory (e.g. for mapped files) is allocated implicitly, but there, too, the amount of memory is determined by the size of the resource.