Assume that the page table for the process currently running on the processor looks as shown in the figure below. All numbers are decimal, all numbers starting with 0 and all addresses are memory syllable addresses. The page size is 1024 bytes.
Which physical address (if any) does each of the following logical (virtual) addresses correspond to? Indicates if a page error occurs while translating the title.
Which physical address (if any) does each of the following logical (virtual) addresses correspond to? Indicates if a page error occurs while translating the title.
a) 1085
b) 2321
c) 5409
number of pages
valid/invalid bit
number of frames
0
1
4
1
1
7
2
0
-
3
1
2
4
0
-
5
1
0
I don't want the solution for this problem, I want someone to explain how this kind of problems are solved.
I think you can guess most configuration from the question. I'll take a) as an example. Maybe you can tell me if I get the answer right and then you can solve the rest by yourself?
The first step is to determine what is the part of the virtual address representing the offset in the page table, and the part representing the offset in the physical frame. For address 1085 and page size of 1024 bytes, you need 10 bits for the offset in the physical frame and the rest for the offset in the page table.
1085 decimal = 0x43D = 0b100 0011 1101
The ten least significant bits (to the right) are the offset in the physical frame. That is 0b00 0011 1101 = 0x3D = 61 decimal. So now you know that the offset in the physical frame will be 61 bytes.
To calculate in what page this offset will be, you take the leftover bits (to the left). That is 0b1 = 0x1 = 1 decimal. This references page table entry 1. Page table entry 1 has the valid bit set. It means that the page is present in memory and will not cause a page fault. The page table entry points to frame number 7. There are 7 frames before frame 7: frames 0, 1, 2, 3, 4, 5, and 6. Thus this virtual address should translate to 7 * 1024 + 61 = 7229.
Related
The image is relating to an example of translating in virtual memory. The address of phys. mem. starts from 0x000 ~ 0x0FC, then moves start 0x100 ~ 0x1FC and so on. Why don't it go like 0x000 ~ 0x0FF, and then 0x100 ~ 0x1FF etc. What are the two lowest bits stand for?
Thank you for your answers. This photo came from MIT open course, and they didn't reveal more details about the address. But I finally figured it out in the later example of the courses.
The two lowest bits can always be zero as the following example:
Supports that we have:
4GB of MM size.
64 lines of cache.
ONLY 1 WORD = 4 bytes PER CACHE LINE.
The address have 32 bits because of 4GB of MM.
The partial address defining the line have 6 bits because of 64 lines of cache.
And because the cache size is 2^6*4B
=> The tag have 24 bits (log2(4GB/2^8B))
=> The lowest bits have 2(32 - 24 - 6) bits.
Because there is only a word per block so that the lowest bits, which act as a data boundary(This is what the course said), are always 0.
Consider the following :
In a system, if virtual address = 32 bits, physical address = 24 bits, and the page size is 8KB.
Now we need to calculate the number of entries in the page table , my answer is as follows :
Here the page size is 8kB meaning that the offset is 13 ( 2^13=8K) , so now we have the logical address is 32 bits meaning that the page offset bits are 32-13=19, so therefore the page table will have 2^19 entries . Is that right ?
That would be 2^32 / 2^13 = 2^19 entries indeed.
The following parameters apply to a system employing a 40-bit virtual address and
1G bytes of physical (main) memory. Word size is 64 bits (8 bytes). Addresses point
to bytes and are aligned on byte boundaries. We use the following notation for an i-bit
address: Ai-1...A2,A1,A0 where Ai-1 is the most significant bit of the address and A0
is the least significant bit of the address. The virtual address is denoted by V39-V0
and the physical address is denoted by P29-P0.
Page size: 64 K bytes
Page table: three-level page table
The virtual page number is split in 3 fields of 8 bits each.
Entries in all tables are 32 bits (4 bytes).
This is what I have found so far,
Since it is a 40 bit virtual address and the Page Size is 64kB (2^16), 16 bits are for offset and we subtract 16 from 40. The remaining 24 bits are for the Virtual Page Number (VPN). The VPN is split in 3 fields of 8 bits each. So we have a three level page table. Each table has 2^8 entries and the size of each table is 2^8 * 4 bytes = 1024 bytes.
From here how would we proceed and find the total amount of virtual memory covered by one entry of page tables at each level?
At the lowest level each entry points to a single page, so working out the amount of virtual memory is trivial, its the size of 1 page. At each of the higher level, one entry represents n entries in the lower table (2^8 in this case). So for the second level its n * amount covered by a bottom level entry, or 2^8* the size of a page. Then use the size of a second level to repeat this calculation for the third level.
I have trouble doing this small exercise:
So far I got this:
For VADDR = 0x5ddb, binary representation is 0101 1101 1101 1011, thus we know the VPN = 101 = 5.
What's the next step?
The most significant three bits constitute the virtual page number, the remaining twelve bits form the offset into the page frame.
In your concrete example the virtual page number is 5, as you correctly mentioned, and the offset is
1101 1101 1011 = 0xddb = 3547
Now proceed like this:
Use the virtual page number as an index into the page table. The 5th (starting from zero) is 0x80000006.
Check the validity bit. It's set, so the page entry is valid. If it was not the page would not be in memory and a page fault would occur.
As said in the image, the rest of the entry is the page frame number. It's the 6th page frame, so you can calculate the page frame's phyiscal address by multiplying this number with the size of a page frame, that is, 4 KiB. Hence, the physical address is
6 * 4 KiB = 24 KiB = 24576
Add the offset to the physical address of the page frame:
24576 + 3547 = 28123
And you have your address.
The virtual address 0x5ddb corresponds to the physical address 28123 = 0x6ddb on the described system.
I'm looking over some exam papers for Operating Systems and I have come across a question which I simply cannot figure out. The memory management scheme is paging
Here is the question:
An operating system that runs on a CPU with a 16 bit address pointer employs a paging memory management scheme with a page size of 1024 bytes.
a) At most how many frames can physical memory contain?
b) Indicate which bits in an address pointer are used for page and offset.
c) A process image of size 3.5K resides in memory. You are given the page table of this process in Figure 1 below. What physical address will the hexadecimal logical address 0x0FCE result in? Show your calculations.
d) How much internal fragmentation does this process produce?
Page Frame
0 4
1 8
2 9
3 6
Figure 1 Process Page Table
Can anybody help me with this ?
A 16bit address bus allows to access 2^16 = 64kB of physical memory. Since on this system you have pages of size 1024B = 2^10, your memory falls into 2^16 / 2^10 = 2^6 physical frames.
Given the previous result, with pages of 1024 = 2^10 bytes, you need 10 bits for accessing any bytes of the page. Thus, the 6 high-order bits ares used for getting the page index from the page table (basically the figure 1 in your homework), and the 10 low-order bits are used for offsetting in that page.
The logical address 0xfce resides in the fourth page because the six high-order bits are 000011b = 3 = 4th page = 0x0c00-0x0fff. Given the page table and assuming the physical memory is sequential, the fourth page maps to the sixth physical frame which start at 1024 * 6 = 0x1800 = 0001100000000000b. The six high-order bits of the page are 000110b, where we add the 10 bits of offset resulting from the previous answer: 000110b << 10 | 0x3ce = 0x1bce.
Since the frame allocation is not sequential (4, 6, 8, 9), the hole between pages 4 and 6 (i.e. 1024B), and the hole between page 6 and 8(i.e. again 1024B), result in physical memory fragmentation.
Hope this help.