Every answer so far is valid for sectors with 4 blocks. However, I cannot find in the spec or in any existing answer how is the access bits configured for higher sectors with 16 blocks?
After spec googlings and readings, I read in in a spec which has the below table:
Therefore, for sectors 32-39 in Mifare 4k, the access conditions is no longer per block but instead shared by blocks as outlined in the above table.
Related
I'm new to computer architecture and am having some trouble with this question:
A hypothetical microprocessor having 12-bit instructions is composed of three fields: the first 4 bits are reserved for the opcode, the next two bits are reserved for a register number and the remaining bits contain the operand memory. What is the maximum memory size, maximum number of different operations the system would be able to understand and the maximum value of an unsigned integer?
There’s not enough information to answer that question. You provided specs about the instructions but not about address size or data word size. The only thing we can say for sure is that 4 bits are enough to specify 16 different instructions.
Suppose we have a 64 bit processor with 8GB ram with frame size 1KB.
Now main memory size is 2^33 B
So number of frames is 2^33 / 2^10 which is 2^23 frames.
So we need 23 bits to uniquely identify every frame.
So the address split would be 23 | 10 where 10 bits are required to identify each byte in a frame (total 1024 bytes)
As it is word addressable with each word = 8B, will the address split now be 23 | 7 as we have 2^7 words in each frame?
Also can the data bus size be different than word size ?
If suppose data bus size is 128 bits then does it mean that we can address two words and transfer 2 words at a time in a single bus cycle but can only perform 64 bit operations?
Most of the answers are dependent on how the system is designed. Also there is bit more picture to your question.
There is something called available addressable space on a system. In a 32 bit application this would be 2^32 and in a 64 bit application this would be 2^64. This is called virtual memory. And there is physical memory which commonly refereed as RAM. If the application is built as 64 bits, then it is able work as if there is 2^64 memory is available. The underlying hardware may not have 2^64 RAM available, which taken care by the memory management unit. Basically it breaks both virtual memory and physical memory into pages( you have refereed to this as frames) and keeps the most frequently used pages in RAM. Rest are stored in the hard disk.
Now you state, the RAM is 8GB which supports 2^33 addressable locations. When you say the processor is 64 bits, I presume you are talking about a 64 bit system which supports 2^64 addressable locations. Now remember the applications is free to access any of these 2^64 locations. Number of pages available are 2^64/2^10 = 2^54. Now we need to know which virtual page is mapped to which physical page. There is a table called page table which has this information. So we take the first 54 bits of the address and index in to this table which will return the physical page number which will be 2^33/2^10 = 23 bits. We combine this 23 bits to the least 10 bits of the virtual address which gives us the physical address. In a general CPU, once the address is calculated, we don't just go an fetch it. First we check if its available in the cache, all the way down the hierarchy. If its not available a fetch request will be issued. When a cache issues a fetch request to main memory, it fetches an entire cache line (which is usually a few words)
I'm not sure what you mean by the following question.
As it is word addressable with each word = 8B, will the address split now be 23 | 7 as we have 2^7 words in each frame?
Memories are typically designed to be byte addressable. Therefore you'll need all the 33 bits to locate a byte within the page.
Also can the data bus size be different than word size ?
Yes you can design a data bus to have any width, but having it less than a byte would be painful.
If suppose data bus size is 128 bits then does it mean that we can
address two words and transfer 2 words at a time in a single bus cycle
but can only perform 64 bit operations?
Again the question is bit unclear, if the data but is 128 bits wide, and your cache line is wider than 128 bits, it'll take multiple cycles to return data as a response to a cache miss. You wont be doing operations on partial data in the cache (at least to the best of my knowledge), so you'll wait until the entire cache line is returned. And once its there, there is no restriction of what operations you can do on that line.
On reading through disc structure, I come across this statement that blocks size is a multiple of sector size. First thought is why do u even need blocks when u have sectors, and secondly why is the block size a multiple of sector like 1,2,4?
Why can't it be half of sector? What's the rationale here? This is not for homework.
Block is an abstraction of filesystems. All filesystem operations can be accessed only in multiple of blocks. In other terms , smallest logically addressable unit to filesystem is block , not a sector.
The smallest addressable unit on a block device is a sector.The sector size is physical property of a block device and is the fundamental unit of all block devices.
Most block devices have 512-byte sectors (although other sizes are common. For example, some CD-ROM discs have 2-kilobyte sectors) while block sizes are commonly of size 512 bytes , 1 KB or 4KB. This is the reason block size is a multiple of sector.
Early in the computing industry, the term "block" was loosely used to refer to a small chunk of data. Later the term referring to the data area was replaced by sector, and block became associated with the data packets that are passed in various sizes by different types of data streams.
read more here: http://en.wikipedia.org/wiki/Disk_sector
I have a question that I am trying to answer that gives the following situation:
16K Pages
32-bit Virtual Addresses
512MB hard disk, sector-addressable with 16K sectors
8 processes currently running
I am asked:
i) How many process page tables are required?
I think this is a trick question? Surely the answer is just 1.
ii) If a process address register PAR can be up to 32 bits, what is the maxmimum amount of physical memory that can be supported on this machine?
iii) How wide in bits should each entry in a process table be if 64MB physical memory is installed?
Please could anyone give me help/hint with the last two parts as I'm really stuck on them? Thanks!
In case you look on here before the exam later today, it is because it doesn't mean Process address register, it means Page address register!
Try looking at http://cseweb.ucsd.edu/classes/fa03/cse120/Lec08.pdf for some more information including help about segmentation and paging combined
Also, the book in the IC library called Operating Systems concepts with code 005.43SIL says that each process has it's own process page table and can even be segmented itself!
i) I said 8
ii) Well, 32 bits of virtual memory addressing with 14 bits of offset in the page table (2^14 = 16K page length) means there are 18 bits left for the page number. In 32 bits of PAR, this means 14 bits for the page location. If you multiple the amount of page locations by the page size, you get 2^14 * 2^14 = 2^18 which is 256MB of RAM
iii) I got 30 bits. 64MB is 2^26 divided by the page size is 2^26/2^14 = 2^12 which means 12 bits for the page location. From (ii) I calculated that 18 bits are left in the virtual memory address for the page number meaning that it should be 30 bits wide. I also put a comment that since it should be byte-aliged maybe the extra 2 bits can be used so that we know whether it has been written to and whether it is currently being stored on the disk.
Hope this helps!
While reading one Freescale processor manual I stuck somewhere, which specifies that it is a 32-bit processor.
May I know the exact meaning and logic behind that?
Update:
Does it specify its ALU width or its address width or its register width specifically or all of them together is N-bit each.
Update:
Hope you have heard of Freescale processors. I just came across their site which describes one of their latest Starcore-based processor known as SC3850 as a 16-bit processor. As far as I know, it has 32 bit program counters, including ALU, and 40-bit register width and 2x64 bit address bus width. Also the SC3850 can handle SIMD(2) instructions which are of 32 bit or 64 bit.
For more details please go through this link
One of the major reasons you would care about the register width of the processor is performance. Generally doubling the number of bits doubles the rate at which a processor can move data around, and compute. This is why we're not all using 8 bit processors.
The other major reason is address space. A 16 bit program counter limits you to 64k of address space, and a 32 bit counter limits you to 4 gigabytes. The new 64 bit processors make it possible, if all the address lines are present, to support 17,179,869,184 gigabytes of memory.
Firstly i dont have a definitive answer but i would guess that 8 being a power of 2, is an important factor. Being a power of 2 also means that certain optimisations may be performed by dividing the 8 bits into groups which also means lookup tables can be used for certain operations. 8 bits in the past was also the perfect size when dealing wiht plain old ascii characters. I can imagine that using 5 bit bytes and encoding a string of ascii characters across memory would be a pain.
Please check out the Wikipedia entry on 32-bit processors, from the entry:
In computer architecture, 32-bit
integers, memory addresses, or other
data units are those that are at most
32 bits (4 octets) wide. Also, 32-bit
CPU and ALU architectures are those
that are based on registers, address
buses, or data buses of that size.
32-bit is also a term given to a
generation of computers in which
32-bit processors were the norm.
Read and understand the article - then the answer for N will be obvious.