Analogy between 2 CPU having same Instruction Set Architecture (ISA) [closed] - cpu-architecture

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We have 2 CPU which has this properties-
Clock Rate
CPI
Execution time
No of instructions
MIPS, will always be identical?
If 2 machines have the same Instruction Set Architecture, which of the upper mentioned property will be same?

4 will be true (same dynamic instruction count) unless the program has speed-dependent behaviour (e.g. keep looping checking the time until 0.1 seconds have elapsed, or other more interesting examples you could come up with).
No reason for 1 to be true, and it's very easy to find counter-examples if you go to any online computer store and look at different models of the same generation of x86-64 CPUs with different max clock speeds. And across different generations, there can be even larger differences in clock speed, e.g. a 25MHz 80386 vs. a 5GHz Zen 2 or Coffee Lake.

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NN stock prediction [closed]

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I'm working on school project for NN(neural network) stock prediction I have my yahoo price market data and I normalised my data to number between -1 to 1 my inputs are date and close however I'm not sure what my output should be (I don't know enough knowledge about stock and market) I was thinking of having date and open as my inout and close as my output. I'm planning on using MLP for my project , but is there anything else I need to do after normalisation. I'm not expert on NN I'm taking this course to rise my total grade we were given only one week to finish this HW so I'm not sure if I'll be able to learn using new software
my inputs are date and open after normalisation what should be the next step
what neural network development tool do you recommend (for mac and PC)
can I use excel NeuroXL add on.. does it work on mac
Thank you

Need help in modelling a delay element in Simulink [closed]

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I need to generate a pulse which steps from 0 to 1 after an initial predetermined time has elapsed. When the new predetermined time is available, the pulse should again step from 1 to 0. It should step from 0 to 1 after that time has elapsed. This model has to be implemented in Simulink.
Thanks.
I'm assuming that the times at which the on/off behaviours are to be performed are available before the model simulation begins. Let's say that it's 2 seconds of value 0 and then 3 seconds of value 1.
Use the Pulse Generator block in the Sources library of Simulink. The trick is starting with a zero. To do this, set the Amplitude to 1 second, the Period to 5s, the Pulse Width to 60% and the Phase Delay to 2s.
The output will look as below.

How to differentiate between Intel Xeon Phi Coprocessors 7120P, 7120X, 7120D, 7120A [closed]

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I have a Xeon phi coprocessor 7120P.
When i run micinfo, i see board SKU to be C0PRQ-7120 P/A/X/D.
I notice that the SMC HW Revision states Product 300W Passive CS and i read on tomshardware that P stands for passive cooling for the intel xeon phi familiy devices.
Is this it or is there any other way to tell which device i have on my system 7120 P/A/X or D?
From the specs given on ark.intel.com, all four devices appear to be same.
Can some one elaborate on what are the actual differences between these devices.
The A/P/X/D variants of the Intel Xeon Phi Coprocessor 7120 are different form factors with different cooling. The codes are: A = active, that is, with fan; P = passive, that is, air stream needs to be supplied from chassis fans; D = dense, special form factor for very dense design; X is a special form factor for manufacturers that want to make their individual designs.
The CPU and memory of these coprocessor versions is the same in all four cases.
Cheers,
-michael

How micro processor is controlled..? [closed]

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How micro processor is controlled? For example, after receiving instructions from memory, the instruction decoder decodes the instruction(???), and the decoded instruction is executed in ALU. How all this happen in a sequence?
At a high level, when the microprocessor is given electricity, it sets the program counter to a predefined address in memory where it expects the sequence of program instructions to start. Each instruction tells the microprocessor to do one or more things, such as read/write memory, do math, or change the value of the program counter.
The ALU is the Arithmetic Logic Unit, which just does the math bits.

simulate dice with fair coin flip [closed]

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Given a fair coin (0/1), how do you simulate fair dice(0 to 5)
Obvious answer I know is toss 3 times, treat each toss as a bit to produce (2^3 = 0 to 7)
If result == 7, discard and repeat.
Well, theoretically worst case big-O of this is really bad (another question in itself, something to do with monte-carlo algos). Lets keep this soln on shelf.
So now my question is,
Is there/can there be n number of coin toss that can guarantee simulation of dice ?
Of course if exists would like to know minimum number of tosses. :)
In absence of a number that is both divisible by three and 2^n, I couldnt think of any way to solve this. :(