I am wishing to use the Sync FIFO interface of a FT232H on a custom board from python on a RaspberryPi. I would use PyFTDI, but PyFTDI doesn't implement the Sync FIFO interface mode. The constant for the Sync FIFO mode is defined in PyFTDI but never used. I plan on accessing Sync FIFO by using PyUSB directly with PyFTDI as a reference. However as PyFTDI doesn't ever use the Sync FIFO mode, I don't know what FTDI commands are used for the mode on the USB endpoints. The documentation I have been able to find from FTDI tell how to use the proprietary library as opposed to the low level command structure actually sent to the chip. I have done a bit of searching, but FTDI provides many documents and it is a bit of information overload.
Does anyone know where the documentation is which covers the low level command codes and arguments which are sent to the FTDI USB end points? I am assuming the authors of PyFTDI were referencing something besides wire sniffing.
According to their knowledge base FTDI provides an API document under an NDA for some circumstances.
In some circumstances, it may be desirable to develop a custom driver for an exotic operating system or an embedded system. In these circumstances, an API document may be obtained from FTDI under NDA to allow driver development for FTDI devices. To request a copy of the API document, please contact FTDI Support support1#ftdichip.com.
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I'm interested in the details of how operating systems work and perhaps writing my own.
From what I've gathered, the BIOS/UEFI is supposed to handle setting up the hardware, and do things like memory-mapping (or IO ports for) the graphics card and other IO devices like audio and ethernet.
My question is, how does the kernel know how to access and (re)configure these devices when it's passed control from the bootloader? Are there just conventions like 'the graphics card is always memory mapped from X to Y address space'? Are you at the mercy of a hardware manufacturer writing a driver for an operating system which knows how the hardware will be initialized?
That seems wrong, so maybe the kernel code includes instructions which somehow iterate through all the bus-connected devices. But what instructions can accomplish that? Is the PCI(e) controller also a memory-mapped device? How do you begin querying and setting up the system?
My primary reference has been the Intel 64 Architectures Software Developer's Manual, which has excellent documentation on how the CPU works, but doesn't describe how the system is setup.
I never wrote a firmware so I don't really know how that works in general. You probably have some memory detection done like an actual memory iteration that is done and some interrogation of PCI devices that are memory mapped in RAM. You also probably have some information in the Developer's manuals as to how you should get some information about memory and stuff like that.
In the end, the kernel doesn't need to bother about that because the firmware takes care to do all that and to provide temporary drivers before the kernel is set up completely.
The firmware passes information to the kernel using the ACPI tables so that is the convention you are looking for. The UEFI firmware launches the /efi/boot/bootx64.efi EFI app from the hard-disk automatically. It calls the main function of that app often called the bootloader. When you write that application, often with frameworks such as EDK2 or GNU-EFI, you can thus use the temporary drivers to get some information like the location of the RSDP which points to all other ACPI tables.
The ACPI convention specifies a language that is AML which, when your kernel interprets, tells it all about hardware. You thus have all the required information there to load drivers and such.
PCI (which is everything nowadays) is another thing. It works with memory mapped IO but the ACPI tables (the MCFG) is helpful to find the beginning of the configuration space for PCI devices that take the form of memory mapped registers.
As to graphics cards, you probably don't want to start with those. They are complex and, at first, you should probably stick to the framebuffer returned by UEFI and at least write a driver for xHCI which is the PCI host controller responsible to interact with USB including keyboards and mouses.
Is it possible to access external hardware without using a driver, i.e. not having the driver abstraction layer in between program and external device?
Can you use a device by implementing your own driver-like controlling/handling directly in your program code?
I'm trying to understand a program that implements a Modbus protocol and some very specific Modbus configurations. Now I don't know how exactly it communicates with the Modbus devices.
It looks to me that this is very similar to what a driver does.
But can it even communicate DIRECTLY with the device without having a driver installed?
Yes, there are several micro-kernel OS's that always configure this way -- drivers are entirely implemented outside of the kernel.
The first thing you likely need is to get access to the device's registers; typically performed with mmap(), you may need to dig around a bit to find the right settings for cacheability, etc...
Second problem is interrupts. Unless you are running something like QNX, you won't have a way to have interrupts signal your program directly. You will probably have to turn them off and poll the device periodically.
If you are using linux and need io ports (inb, outb, etc...) man ioperm for more information.
Many STM32 chipsets support 1 or 2 channel CAN PIN Outs.
Is there a CAN bus library for STM32 to direct connect with a CAN transceiver such as MCP2551? But it does not matter what the CAN transceiver is.
A CAN transceiver is just a high speed step down converter. (on a basic level)
CAN protocol works in a variant of voltage ranges. MCP2551 is a set CAN transceiver suitable for 12V and 24V systems. With added features to help with the physical layer like externally-controlled slope for reduced RFI emissions, detection of ground fault, voltage brown-out protection, etc.
It has no dependency on the CAN logic. It is just to help you with the bare physical layer.
To answer your question:
As RishabhHardas recommended, use the HAL library provided by STM32 through CubeMx.
Using CubeMx
This is a software provided by ST-Micro to help you setup the boilerplate code for any peripheral application.
You can also check out the examples projects provided by STM in the Cube. This will give you a kick-start in understanding CAN on STM32
STM32Cube_FW_F4_V1.9.0\Projects\STM324xG_EVAL\Examples\CAN\CAN_Networking
After setting it up, you'll be able to call HAL_CAN_Transmit() and HAL_CAN_Receive() by including the header.
Check out this discussion on STM32-Community.
For software, look for the CANtact open source project on Github. It is an implementation for the STM32F042. I had to adapt the project to build it under Atollic but it was not too hard and it works. It provides a SLCAN type of interface over a virtual COM port over USB, which is very fast and convenient.
There is also CAN code for the STM32F103 (Bluepill) (Google "lawicel-slcan") but that chip is not as convenient because you cannot use both CAN and USB at the same time (they share RAM buffers) so if you want CAN, you will not have USB, and routing the CAN messages over a UART will severely limit the bandwidth. That may be OK if your entire application runs on the STM32.
I have several years experience with microcontroller programming. Freertos provides the necessary code to port to a set of microcontrollers. I would like to port Freertos to an embedded system which is not supported.
Which main steps have to be undertaken in order to successfully port freertos to another embedded system? (for example: what initialization steps should absolutely be done in port.c etc...) I have read the freertos page about porting, but it is still pretty vague.
I presume this is the page you are referring to http://www.freertos.org/FreeRTOS-porting-guide.html it is vague because each architecture has its own requirements. For example, is a yield going to be performed synchronously using a trap style instruction, or asynchronously using a pended interrupt, how is interrupt nesting going to be implemented and what support does the hardware give to implement it, etc. Therefore it would have helped a lot if you said which architecture you wanted to port to, then I might have been able to suggest which port to look at as a reference.
I want to build a microcontroller-based CAN node card that has interfaces like UART, SPI and I²C, to which connect different peripherals and interfaces, like say a EIA-485 counter or a SPI digital I/O expander. I'd like to define a profile for the card that's flexible enough to adapt to any possible configuration and include any device that can be connected to such node card. Since CANopen profiles seem to be pretty rigid, I researched CANopen virtual devices but that seems not the answer either.
Is there a standard for such functionality or I'm sailing unknown waters?
You are sailing unknown waters unless you consider a CANopen bootloader a possible solution. There is no existing device profile that fits your criteria. CANopen is remarkably flexible but arbitrary extensibility is beyond it.
You could export the registers of your microcontroller 1:1 through the object dictionary and issue interrupts through PDOs. It would certainly be a fun exercise if just a bit impractical.
From the CAN in Automation website:
CANopen generic I/O modules are standardized in the CiA 401 device
profile specification. The profile supports a granularity of 1-, 8-,
16-, and 32-bit for digital I/Os and a resolution of 1-, 2-, and
4-byte for analog I/Os.
However, it may be easier to implement a custom device, based on the general CiA 301 CANopen application layer and communication profile standard. You could implement a set of general purpose IOCTL functions using Manucturer objects (2000h to 5FFFh) and possibly use SDO Block Transfer to 'stream' data to specific OD objects representing connected device end points.
You will need to consider that, even with a bitrate of 1 Mbps at the physical layer, the CANopen protocol is never going to be able to keep up with a USB2 HS device when it comes to streaming data! Also bear in mind that if you use PDOs for 'real-time' exchange of OD values there will be a significant lag and that the time quantum for PDO exchange is in the order of 25 ms or greater.
The final consideration is what CANopen master are you going to use? If the product is to be commercially available then you will need to specify and document your EDS very carefully (maybe even providing an OPC or similar API).