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I am trying to perform Power Analysis (Side-Channel Attack) on AES-128 that I have implemented on STM32F407 DISCOVERY MCU. I have found out that I can measure with a current probe from VCap1 and Vcap2 . To do so, the regulator that feeds the core should be turned off and the processor should be fed with external power supply to minimize the noise. But the regulator is inside the core and I cannot take it off. How can I de-activate the regulator? Or is there any other way to perform Power Analysis on STM32F407VG MCU?
I afraid it is not possible. The voltage regulator has to be on otherwise the core and peripherals clocks will not work. There is no way to switch this regulator off
You need to find another way.
The datasheet mentions that, on some packages, there is pin called BYPASS_REG which can be used to disable internal voltage regulator and allow you to supply core using V_CAP pins. See Section 2.2.16 Voltage Regulator in the STM32F407 datasheet (DS8626).
Unfortunately, STM32F407V present on Discovery Board isn't one of the packages which feature BYPASS_REG pin. This pin is present on WLCSP90, UFBGA176 and LQFP176 packages, according to Table 3. Regulator ON/OFF and internal reset ON/OFF availability.
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I have 3 monitors with different refresh rate and I want to play games on the monitor with the highest refresh rate. Can I do it without cutting its refresh rate down to match the other monitor's refresh rate?
That is possible.
FYI:
Monitor's aren't dependent on each other's FPS. You can have 3 monitor's with each its own refresh rate. There is no such thing as "cutting its refresh rate down". You simply need to set them up correctly within your OS's settings.
As long as your monitor is correctly set-up and it's refresh rate is set at its max. Within the game(s)'s options, you need to specify the monitor that you want to use ( I assume the one with the highest FPS).
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I have made a simple relay board using a 12vdc Bosch automotive relay.
The relay works great, Comm/NO being successfully controlled with RPi GPIO(25) using a 3+ RPi.
However, the only wire from RPi to relay board is the GPIO (initiated as GPIO.out) with no ground from RPi to relay board. So, is the grounding necessary?
I have researched and found multiple threads saying GPIO's do not need a ground return; others saying the opposite.
Here is the diagram:
Relay board diagram
Probably it needs to be grounded. At least nothing bad will happen.
The grounding happens indirectly over the power supply of the RPi and the power supply of the relay. While this may work, it is dangerous and may fry either part.
As there is no guarantee that the two PSUs generate a common ground, you may have undesired current flowing through the GPIO wire. The resistor there gives some protection, but this might not be enough to prevent frying your Pi. You might get a more detailed answer on the possible problems on https://electronics.stackexchange.com.
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For an ethernet connection between 2 points which will be used as point to point communication (for embedded devices). Is internet connection, hubs or switches are really necessary? Or can we still send and receive data from one MCU to another one by using ethernet without using any internet connection, hubs or switches?
There's certainly no need for an Internet connection.
If you want to connect two computers together directly, then you will need to use a crossover cable rather than a patch cable unless the devices you are using support auto MDI-X.
Putting a cheap hub between them will probably be simpler.
No, they are not necessary. We ofen do this between either two of "product board", "FPGA board", and "PC" when debugging ethernet Tx/Rx issues.
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Why do we need to ENABLE a GPIO clock by RCC_AHB register when we are using of that GPIO as a Peripheral Input/Output pin?
For instance for STM32F407 ADC1, it has its own clock and samples the data presents on the pin by its inside defined clock through the RCC_APB register and prescaler. So i think there is no need to enable GPIO Clock, but it doesn't work in this way.
So the question is what is the job of GPIO clock generally?
Because it was designed this way. Why? To save the power if the peripheral is not used.
GPIO clock enables the control part of the GPIO, allowing you for example to enter the analog mode, and power the input transistors.
https://fastbitlab.com/input-configuration-microcontrollers/
The gpio is connect to input data register and output data register,etc. The register need the clock to read and write, not the gpio itself.
I hope I've interpreted it correctly.
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Some media have reported that a new hardware bug in Intel processors, allowing user mode processes to access kernel mode memory, has been discovered:
It is understood the bug is present in modern Intel processors
produced in the past decade. It allows normal user programs – from
database applications to JavaScript in web browsers – to discern to
some extent the layout or contents of protected kernel memory areas.
The effects [of fixes] are still being benchmarked, however we're
looking at a ballpark figure of five to 30 per cent slow down,
depending on the task and the processor model.
After the bug is fixed, which slowdown am I to expect for multicore floating point computations?
To my understanding, only the performance of switches between kernel and user mode are affected. For example, handling a lot of I/O is a workload where this is frequent, but CPU-intensive processes should not be affected as much.
To quote from one article that analyzes performance of the Linux KPTI patch:
Most workloads that we have run show single-digit regressions. 5% is a good round number for what is typical. The worst we have seen is a roughly 30% regression on a loopback networking test that did a ton of syscalls and context switches.
...
So PostgreSQL SELECT command is about ~20% slower with KPTI workaround, and I/Os in general seem to be impacted negatively according to Phoronix benchmarks especially with fast storage, but not gaming performance, Linux kernel compilation, H.264 encoding, etc…
Source: https://www.cnx-software.com/2018/01/03/intel-hardware-security-bug-fix-to-hit-performance-on-windows-linux/
So, if your FP computations rely mostly on in-memory data shifting and not I/O, they should be mostly unaffected.