Here's my configuration:
GPIO_InitTypeDef GPIO_InitStruct = {0};
GPIO_InitStruct.Pin = 8;
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
When I put the signal on the input pin (square, 2Hz, 3.3Vp-p) I get an interrupt every 250ms, so - on every RISING and falling edge of the signal. I changed the test signal duty cycle to test if it's really what is happening and it confirmed it. I get the interrupt on both edges.
I even debugged the HAL driver to test if it does what I think it does. And yes, it seems to configure the EXTI correctly, only for the falling edge for my pin.
What may be the cause of such behavior? My device is STM32H747I-DISCO discovery board with TouchGFX software used for presentation. The software works correctly, I tested it on measuring the time between other timer interrupts.
I monitor the test signal on the oscilloscope to ensure the input signal on my pin is correct. I tried to use another pin on the same port, but I observe identical behavior. I get interrupts on both rising and falling edges of the signal, despite the pin is configured to trigger the interrupt only on the falling edge.
I also tested the case with the rising edge only. Also in this case I get the interrupt on both edges.
The problem turned out to be a hardware error, a voltage spike I overlooked. The STM32 EXTI input worked correctly all the time. There was indeed a spurious falling edge.
Simulated problem illustration, the 10n capacitor causes voltage spikes and spurious edge detection. In the real circuit, when a digital oscilloscope was used and the time base was too long to capture the spike - the signal looked like a proper square wave. After shortening the time base I noticed the spike. As it is shown on the illustration, this behavior can be easily simulated in a circuit simulator:
SIMULATION LINK
Removing the capacitor from the circuit solved the problem.
To avoid getting noise and other spurious signals on the input shielded wires can be used. The real world circuit was tested and it works properly without the capacitor.
The opto-coupler is just a simplified model of the optical sensor used in the real machine.
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who do someone know about the STM32 GPIO toggling timing issue?
I want get the always normal togging timming signal without the abnormal togging timming iusse.
Due to the contacted image, I have a diffcult problem that the signal timing of the One Wire protocol changed the total timing in order to decided the period of the One wire logic interface.
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_12);
DWT_Delay_us(2); // about 2us delay time
using the STM32F722 mcu and STM32 CUBEMX/IDE
I have been studying about SPI and would like to clarify few more things:
1.
I am trying to understand about CPOL and CPHA in particular:
I have a device (MCP41 that I want to write SPI drivers for). The datasheet can be found here:
https://ww1.microchip.com/downloads/en/devicedoc/11195c.pdf
According to the timing diagram:
It mentions that Data is always latched in on the rising edge of the SCK. Is that supposed to give me any hints about CPHA?
It also mentions that the Data is always clocked out of the SO pin after the falling edge of SCK. Since it mentions falling edge of the SCK, I understand that the CPHA for this device should be set to 1, is that correct?
2 What if I have 2 SPI devices connected to the same SPI bus. One device requires CPOL = 0, CPHA = 0 and the other device requires CPOL = 0 and CPHA = 1. Does that mean it will not be possible to communicate with both devices via single SPI bus?
The timing diagram shows that this device requires SPI mode 0: CPOL=0 CPHA=0.
The way to read the diagram is that the clock idles low, so CPOL=0. The data is sampled (called "latched" above) on the rising edge. This is the first edge when starting low so CPHA=0 (the rising edge would be the second edge if starting high).
The comment about output data on the falling edge simply means that the device outputs the next data starting on the second edge of the preceding pulse, this way it is ready in time for the first edge of the next clock pulse.
For your second question, yes you can mix different clock modes (polarity, phase and speed) on the same bus, as long as you make all the changes when no device is selected, ie: when all chip-selects are high. You may want to even change the mode of the chip select pins momentarily to GPIO while you deconfigure and reconfigure the SPI peripheral (I'm never sure what alt-function pins will output while you are messing with the registers of a disabled peripheral).
We are using STM32CubeMX to generate the initial code for ADC pin-matching.
In our particular case, all of the 16 available pins- that is, PA0 to PA7, PB0 to PB1, and PC0 to PC5- in the ADC1 mode are used. It is interesting yet absurd to find that while all the other pins generate the normal voltage values(varing from 1500 to 3000), PB0 outputs 0 constantly and PB1 outputs 4040 averagely.
We have examined multiple times and we are pretty sure the problem isn't on our external sensor. Meanwhile, we have used a second board(identical model number), however, the same issue reoccurred. We exerted ourselves to fix the problem yet still trapped by it.
CubeMX initialization pic1
CubeMX initialization pic2
i was trying interrupt on PA0 and PB5 pins on stm32f103c8 board(with cubemx generated code),but when triggered square wave impulse on B5 the along with ISR of EXTI9_5_IRQHandler the isr of A0 also getting executed EXTI0_IRQHandler.
.No jumper wires are involved direct probe connection from signal generator is used(siganls are generating fine cross verified with oscilloscope).Tried checking up with oscilloscope on A0 pin,while giving trigger wave to B5,no changes are seen on A0 pin.Then also isr gettting executed but the vise versa didnt happen.
Tried with stm32l152 discovery board the same thing there also the wrong isr are also getting executed.(0th and 5th pin of different ports but).When checked the EXTI->PR REGISTER while in debugging mode ,The bits of 0,1,5 are set when trigger wave given to pin 5.Even though the pin1 nor its interrupts settings are not intialized its also getting set.
Spend almost two days till now debugging this issue, any help will be thank full.Till now tried F1 and L1 SERIES both are having issue
The clock configurator in STM32CubeMX does not allow the PLL divider DIVP1 frequency to exceed 300MHz so it is impossible to use it to achieve the board's maximum of 480MHz. To do this you must go into the code for the configurator and manually change the multipliers. Is this confusion on my part or an error with the data provided by ST for the board?
Checking CPU performance singing a hardcoded assembler timing loop the subtract and branch instructions of the timing circuit take two clock cycles. On my Nucleo-H723ZG board these two take a total of one cycle. Is DUAL ISSUING not available on H743?
Once again in the STM32CubeMX in the System RCC section Master_Clock_Output_1 is highlighted in RED. (Conflict with: USB_OTG_FS: Activate_SOF). What is this all about?
You need to have the correct voltage scale (VOS) which affects the maximum clock directly. To clock this device at 480MHz.
As for your pin conflict - the MCO pin is a clock output to use for clocking external devices. Pins in the STM32 chip can be multiplexed such that they can serve multiple functions, such as ADC1_CH4 GPIO_OUT etc... You have a conflict that 1 pin is trying to facilitate 2 functionalities, and such you have a conflict. rearrange the functionality or pin to fix the conflict.