I understand that [-> m] is a non-consecutive GoTo operator and can be used as (e.g.)
#(posedge clk) a |=> b [->2] ##1 c;
But I came across an example, where I see (in the middle of a property), a -> b. What does that mean? Does it mean if a is true that b is true? Does it behave like an overlapping implication operator? Please see the example below. Thanks.
property count_event(reg [15:0] PerfCtr, reg [15:0] event_count);
#(posedge DfiClk)
disable iff (disable_perfcntcheck)
((PWR_OK === 1'b1) && (Reset === 1'b0) && (DebugPerfCtrEn === 1) && (dfi_event_select === 1) && ($rose(dfi_event))) |->
##[1:5] !$isunknown(capture_dly) && (**!capture_dly -> event_count == PerfCtr**) ##1 !$isunknown(capture_dly) && (**capture_dly -> event_count == PerfCtr**);
It looks like it is in the middle of a logical expression, not property. It is the logical implication operator:
11.4.7 Logical operators
The logical implication expression1 –> expression2 is logically equivalent to
(!expression1 || expression2), and the logical equivalence expression1 <–> expression2 is
logically equivalent to ((expression1 –> expression2) && (expression2 –> expression1)).
Each of the two operands of the logical equivalence operator shall be evaluated exactly once.
Related
I have scenario of assertion where first a should be high 1 cycle after this b should be high and 1 cycle after that c should be high, after this with 1 cycle delay d should be high
I am confused as to how these assertions should be coded. I have three options please help me which should be followed as correct solution
Option1 : a |=> b |=> c |=> d ;
Option2 : a |=> b ##1 c ##1 d;
Option3 : a ##1 b |=> c ##1 d;
I am getting stuck at these options which one to follow . Please guide me about best solution and as to why
According to me best coding from description would be
a |=> b |=> c ##1 d
Reason : Operator used is Non overlapping Implication operator which tells if antecedent is true then evaluate consequent at next clock tick.Use of this operator is needed as b has to be high only if a is high else not necessary.so,condition of a is implying condition of b.so is the case with c.
But in case of d, statement says delay which means to use ## to specify number of clock cycles delay.
Option 2 is the only correct option (assuming you want this triggered whenever a is high). Implication is true if the antecedent is false or if the consequent is true.
Option1 : a |=> b |=> c |=> d ; -> If !a, this is true, if a ##1 !b, then this is true, if a ##1 b ##1 !c, then this is true. As soon as the antecedent is false, the whole statement is true.
Basically (b |=> c) is true when b is false, which means Option1 says that if a is high AND if b is high on the next cycle AND if c is high on the next cycle then d must be high on the last cycle. That is not what you need.
Although your question is actually requires a then b then c then d. That would require this:
a ##1 b ##1 c ##1 d
I have the following property:
property p_0;
$rose(signal_a) |-> $rose(signal_b) ;
endproperty
my problem is, after HW RST, signal_b rises (normal behavior) but the assertion fails, and I want this check to be evaluated only later.
I wanted to work with first_match() with something like below:
p_0_a : assert property ( ! first_match(p_0)) else `uvm_fatal(...)
so that I skip the first match of this property but the compiler generates a syntax error.
Is there a way to skip the evaluation of SVAs after specific number of iterations?
Cascaded implication operators may well help you out, for example something along the lines of:
assert property (reset |-> p_0);
Basically, |=> and |-> are right-associative:
A |=> B |=> C
means
A |=> ( B |=> C )
ie If A happens, check (B |=> C) immediately afterwards. If A does not happen, don't check (B |=> C).
I am trying to do something like this:
assert property (#(posedge clk) disable iff (!rst) a[*c] -> $rose(b))
Here c is not a 'constant' but a value coming from some bits of a register. eg: reg[4:0] which is written only once. The check is to see if b is asserted only when a is high for "c" number of cycles.
However, SVAs do not accept a variable like this : [*reg[4:0]]. Any ideas??
Introduce a local variable ctr. At every posedge a new assertion with a new instance of ctr will be created. Set ctr equal to the value in reg1. Check that a is true throughout the down count. Decrement the counter as long as it is larger than zero. The (ctr>0, ctr--)[*0:$] statement will count down until ctr == 0 is true.
You might want to change (ctr>0, ctr--)[*0:$] to (ctr>0, ctr--)[*1:$], depending on what results you expect if reg == 0.
property pr_aRegTimes;
integer ctr;
disable iff (!rst)
#(posedge clk)
(1, ctr = reg1) ##0 a throughout ((ctr>0, ctr--)[*0:$] ##1 (ctr == 0)) |-> $rose(b);
endproperty
as_aRegTimes: assert property (pr_aRegTimes)
else $error("aRegTimes failed");
Working example:
http://www.edaplayground.com/x/Xh9
Sources:
https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/
http://www.win.tue.nl/~jschmalt/teaching/2IMF20/SvaFvTutorialHVC2013.pdf
property pr_aRegTimes;
integer ctr;
disable iff (!rst)
#(posedge clk)
($rose(a), ctr = reg1) ##0 (a&&ctr>0,ctr--)[*] |-> $rose(b);
endproperty
property p_no_glitch;
logic data;
#(in[i]) disable iff (!rst_n)
(1, data = !in[i]) |=>
#(posedge clk)
(in[i] == data);
endproperty : p_no_glitch
CHECK_GLITCH : assert property(p_no_glitch) else $error("%m p_no_glitch");
If the module is disabled I get the following message:
Antecedent of the implication never satisfied
is there a flag (or any other way) to switch off the above message ?
the way to go in VCS is -assert quiet+quiet1+nopostproc. Of course it would be better if the SVA 'owner' would add something like disable iff (!rst_n or !en)
What is the difference between the | and || logical operators in MATLAB?
I'm sure you've read the documentation for the short-circuiting operators, and for the element-wise operators.
One important difference is that element-wise operators can operate on arrays whereas the short-circuiting operators apply only to scalar logical operands.
But probably the key difference is the issue of short-circuiting. For the short-circuiting operators, the expression is evaluated from left to right and as soon as the final result can be determined for sure, then remaining terms are not evaluated.
For example, consider
x = a && b
If a evaluates to false, then we know that a && b evaluates to false irrespective of what b evaluates to. So there is no need to evaluate b.
Now consider this expression:
NeedToMakeExpensiveFunctionCall && ExpensiveFunctionCall
where we imagine that ExpensiveFunctionCall takes a long time to evaluate. If we can perform some other, cheap, test that allows us to skip the call to ExpensiveFunctionCall, then we can avoid calling ExpensiveFunctionCall.
So, suppose that NeedToMakeExpensiveFunctionCall evaluates to false. In that case, because we have used short-circuiting operators, ExpensiveFunctionCall will not be called.
In contrast, if we used the element-wise operator and wrote the function like this:
NeedToMakeExpensiveFunctionCall & ExpensiveFunctionCall
then the call to ExpensiveFunctionCall would never be skipped.
In fact the MATLAB documentation, which I do hope you have read, includes an excellent example that illustrates the point very well:
x = (b ~= 0) && (a/b > 18.5)
In this case we cannot perform a/b if b is zero. Hence the test for b ~= 0. The use of the short-circuiting operator means that we avoid calculating a/b when b is zero and so avoid the run-time error that would arise. Clearly the element-wise logical operator would not be able to avoid the run-time error.
For a longer discussion of short-circuit evaluation, refer to the Wikipedia article on the subject.
Logical Operators
MATLAB offers three types of logical operators and functions:
| is Element-wise — operate on corresponding elements of logical arrays.
Example:
vector inputs A and B
A = [0 1 1 0 1];
B = [1 1 0 0 1];
A | B = 11101
|| is Short-circuit — operate on scalar, logical expressions
Example:
|| : Returns logical 1 (true) if either input, or both, evaluate to true, and logical 0 (false) if they do not.
Operand: logical expressions containing scalar values.
A || B (B is only evaluated if A is false)
A = 1;
B = 0;
C =(A || (B = 1));
B is 0 after this expression and C is 1.
Other is, Bit-wise — operate on corresponding bits of integer values or arrays.
reference link
|| is used for scalar inputs
| takes array input in if/while statements
From the source:-
Always use the && and || operators when short-circuiting is required.
Using the elementwise operators (& and |) for short-circuiting can
yield unexpected results.
Short-circuit || means, that parameters will be evaluated only if necessarily in expression.
In our example expr1 || expr2 if expr1 evaluates to TRUE, than there is no need to evaluate second operand - the result will be always TRUE. If you have a long chain of Short-circuit operators A || B || C || D and your first evaluates to true, then others won't be evaluated.
If you substitute Element-wise logical | to A | B | C | D then all elements will be evaluated regardless of previous operands.
| represents OR as a logical operator. || is also a logical operator called a short-circuit OR
The most important advantage of short-circuit operators is that you can use them to evaluate an expression only when certain conditions are satisfied. For example, you want to execute a function only if the function file resides on the current MATLAB path. Short-circuiting keeps the following code from generating an error when the file, myfun.m, cannot be found:
comp = (exist('myfun.m') == 2) && (myfun(x) >= y)
Similarly, this statement avoids attempting to divide by zero:
x = (b ~= 0) && (a/b > 18.5)
You can also use the && and || operators in if and while statements to take advantage of their short-circuiting behavior:
if (nargin >= 3) && (ischar(varargin{3}))