How to make Synopsys VCS Verdi to show display macro messages in Wave window? - system-verilog

I know that in Questa or Riviera UVM error messages can be indicated in the waveform as well.
With system verilog display macros (but not UVM!), how can an indicator be shown in the Synopsis Verdi waveform when the display happens?
For example lets say something like this macro is used:
`define DELIM
`define DEBUG_PRINT(p0, p1=ELIM, p2=ELIM, p3=ELIM, p4=ELIM, p5=ELIM) \
`ifdef D``p1 \
my_debug($psprintf(p0)); \
`else \
`ifdef D``p2 \
my_debug($psprintf(p0, p1)); \
`else \
`ifdef D``p3 \
my_debug($psprintf(p0, p1, p2)); \
`else \
`ifdef D``p4 \
my_debug($psprintf(p0, p1, p2, p3)); \
`else \
`ifdef D``p5 \
my_debug($psprintf(p0, p1, p2, p3, p4)); \
`else \
my_debug($psprintf(p0, p1, p2, p3, p4, p5)); \
`endif \
`endif \
`endif \
`endif \
`endif
Ideas that may be relevant here to some solution:
I am aware of the TMR capability briefly but I'm not sure if that should be applied here. Neither if it is propagating to the Wave window as an indicator.
If it would be necessary to use some workaround like below (flag/event), since it is not UVM, I'm not sure how to get around the problem (such as discussed here) of applying the semicolon in the middle :
my_debug($psprintf(p0)); \ -> tb.event \

Related

Plantuml generates interface from Doxygen group

I would like to generate an interface diagram using Plantuml in Doxygen. Instead of typing the interfaces one by one as below, is it possible to generate the interface from the Doxygen group? I have created a group called "ExportInterface".
#startuml
interface "interface.h" as interface
{
function1(void): void
function2(void): void
function3(void): int
}
#enduml
doxygen -x Doxyfile
# Difference with default Doxyfile 1.9.1 (ef9b20ac7f8a8621fcfc299f8bd0b80422390f4b)
OUTPUT_DIRECTORY = ms
ALWAYS_DETAILED_SEC = YES
STRIP_FROM_PATH = .
STRIP_FROM_INC_PATH = .
ALIASES = "project=\par Project: \n" \
"subsystem=\par Subsystem: \n" \
"history=\par History: \n\htmlonly <pre>" \
endhistory=</pre>\endhtmlonly \
"startuml{1}=\image html \1\n\image latex \1\n\if DontIgnorePlantUMLCode" \
enduml=\endif \
"xrefreq{2}=#ref \1 \"\1\" #anchor \1 <a href='\2' target='_blank'>Requirements Object Link</a>\n" \
"satisfyreq{2}=#xrefitem satisfy \"Satisfies requirement\" \"Requirement Satisfaction\" #xrefreq{\1,\2}" \
"verifyreq{2}=#xrefitem verify \"Verifies requirement\" \"Requirement Verification\" #xrefreq{\1,\2}" \
"xrefarc{2}=#ref \1 \"\1\" #anchor \1 <a href='\2' target='_blank'>Containing Rhapsody Model</a>\n" \
"xrefarc_path{3}=#ref \1 \"\2\" #anchor \1 <a href='\3' target='_blank'>Containing Rhapsody Model</a>\n" \
"tracearc{2}=#xrefitem architecture \"Architecture\" \"Traced Architecture\" #xrefarc{\1,\2}" \
"tracearc_path{3}=#xrefitem architecture \"Architecture\" \"Traced Architecture\" #xrefarc{\1,\2,\3}" \
"startTraceIt{1}=<B>\anchor \1\nTraceIt data: \1</B><PRE>" \
endTraceIt=</PRE> \
"reftrace{1}=#anchor ref_\1 #ref \1" \
"reftrace{2}=#anchor ref\1_\2 #ref \2"
EXTENSION_MAPPING = fidl=IDL
DISTRIBUTE_GROUP_DOC = YES
TYPEDEF_HIDES_STRUCT = YES
EXTRACT_ALL = YES
EXTRACT_PRIVATE = YES
EXTRACT_STATIC = YES
EXTRACT_ANON_NSPACES = YES
CASE_SENSE_NAMES = YES
SORT_MEMBER_DOCS = NO
WARN_LOGFILE = doxygen-build/warnings.log
INPUT = ../adapt \
../core \
FILE_PATTERNS = *.c \
*.cc \
*.cxx \
*.cpp \
*.c++ \
*.java \
*.ii \
*.ixx \
*.ipp \
*.i++ \
*.inl \
*.idl \
*.ddl \
*.odl \
*.h \
*.hh \
*.hxx \
*.hpp \
*.h++ \
*.cs \
*.d \
*.php \
*.php4 \
*.php5 \
*.phtml \
*.inc \
*.m \
*.markdown \
*.md \
*.mm \
*.dox \
*.pyw \
*.f90 \
*.f \
*.for \
*.tcl \
*.vhd \
*.vhdl \
*.ucf \
*.qsf \
*.as \
and \
*.js \
*.fidl \
*.fdepl
RECURSIVE = YES
EXCLUDE_PATTERNS = *_Template.c
IMAGE_PATH = images
FILTER_PATTERNS = *.fidl=
REFERENCED_BY_RELATION = YES
REFERENCES_RELATION = YES
VERBATIM_HEADERS = NO
HTML_TIMESTAMP = YES
GENERATE_ECLIPSEHELP = YES
GENERATE_TREEVIEW = YES
GENERATE_LATEX = NO
MACRO_EXPANSION = YES
SEARCH_INCLUDES = NO
PREDEFINED = "FUNC(type, memclass)=type" \
"VAR(type, memclass)=type" \
"CONST(type, memclass)=const type" \
"P2CONST(type, memclass, ptrclass)=const type *" \
"CONSTP2CONST(ptrtype, memclass, ptrclass)=ptrtype * const" \
DOXYGEN_SHOULD_SKIP_THIS \
__declspec(x)=
CLASS_DIAGRAMS = NO
HAVE_DOT = YES
UML_LOOK = YES
CALL_GRAPH = YES
DOT_IMAGE_FORMAT = svg
PLANTUML_JAR_PATH = C:\ProgramData\chocolatey\lib\plantuml\tools\plantuml.jar
DOT_GRAPH_MAX_NODES = 500

If YAD is a fork of Zenity why is there no --imagelist?

Zenity is used in many of my bash projects, but looking at the advanced features of YAD there are many reasons to switch. After some testing unfortunately I discovered there is no --imagelist option for the list type dialog. This is a major problem as most of my projects use imagelists.
The below example runs on zenity version 3.28.1
#!/bin/bash
table=(~/image.png " " "Title1" " " "description1" "output1" ~/image.png " " "Title2" " " "description2" "output2" ~/image.png " " "Title3" " " "description3" "output3")
zenity --list --title="page title" --text="some random text" --imagelist --ok-label=Open --cancel-label=Home --print-column=6 --hide-column=6 --separator=' ' --width=600 --height=400 \
--column="Cover image" \
--column=" " \
--column="Name" \
--column=" " \
--column="details" \
--column="Folder" \
"${table[#]}"
the dialog should look like this:
In this example ${table[#]} is an array that contains all the data for each row including the file-path to the image in column 1. Is there a way to do this in YAD?
I installed YAD and looked at all the help pages provided in terminal, also tried to run similar imagelist examples, but it seems to be not supported (syntax is mostly the same as YAD is a fork of zenity)
With yad the columns can have a type associated with them. In your case you want to use the :IMG type for the first column, and the other two can remain as plain text.
table=(
~/image.png "" "Title1" "" "description1" "output1"
~/image.png "" "Title2" "" "description2" "output2"
~/image.png "" "Title3" "" "description3" "output3"
)
yad \
--list \
--title="page title" \
--text="some random text" \
--imagelist \
--print-column=6 \
--hide-column=6 \
--separator=' ' \
--width=600 \
--height=400 \
--column="Cover image:IMG" \
--column=" " \
--column="Name" \
--column=" " \
--column="details" \
--column="Folder" \
--button="Home":1 \
--button="Open":20 \
--response=20 \
"${table[#]}"
The output, missing your images
That will set the exit code to 20 if you press Enter or click Open on a list item, as well as outputting "output1" or "output2" etc.
That said, I have been experiencing issues with the exit codes or output text not appearing correctly. The above example works fine for me, but if I change the the Open exit code to "25" instead of "20" it stops working. No idea why it behaves inconsistently.

error while opening CHM after compiling help using doxygen

I am recently getting the following error while opening CHM file generated by Doxywizard version 1.8.16.
On a Win 7 m/c, I get the following error on all pages:
'$' is undefined
for every page.
it comes from the following line in index.html
$(function() {
initMenu('',false,false,'search.php','Search');
});
UPDATED LATER:
On a Win 10 m/c, i didn't get the above error, but a different error in some pages in the CHM as follows :
Unable to get property 'style' of undefined or null reference
This error happens within the jquery.js file.
--
Diff of configuration is the following (note that I have replaced some names with '...'):
# Difference with default Doxyfile 1.8.16 (cfd73d5c4d1a66c620a3b7c08b72a3f3c3f9
255*)
PROJECT_NAME = ...
PROJECT_NUMBER = x.y.z.w
PROJECT_BRIEF = "..."
PROJECT_LOGO = .../....png
FULL_PATH_NAMES = NO
TAB_SIZE = 8
OPTIMIZE_OUTPUT_FOR_C = YES
TOC_INCLUDE_HEADINGS = 0
EXTRACT_ALL = YES
HIDE_SCOPE_NAMES = YES
SHOW_USED_FILES = NO
INPUT = ../src/ \
../src/main.c \
...
...
../docs/....md \
\docs
FILE_PATTERNS = *.c \
*.cc \
*.cxx \
*.cpp \
*.c++ \
*.d \
*.java \
*.ii \
*.ixx \
*.ipp \
*.i++ \
*.inl \
*.h \
*.hh \
*.hxx \
*.hpp \
*.h++ \
*.idl \
*.odl \
*.cs \
*.php \
*.php3 \
*.inc \
*.m \
*.markdown \
*.md \
*.mm \
*.dox \
*.py \
*.f90 \
*.f \
*.for \
*.vhd \
*.vhdl
RECURSIVE = YES
EXAMPLE_PATTERNS = *.c \
*.h
HTML_TIMESTAMP = YES
GENERATE_DOCSET = YES
GENERATE_HTMLHELP = YES
CHM_FILE = mydoc.chm
HHC_LOCATION = "C:/Program Files (x86)/HTML Help Workshop/hhc.exe"
GENERATE_TREEVIEW = YES
MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest
LATEX_CMD_NAME = latex
LATEX_MAKEINDEX_CMD = \makeindex
INCLUDE_PATH = ../include
HAVE_DOT = YES
CALL_GRAPH = YES
CALLER_GRAPH = YES
DOT_PATH = "C:/Program Files (x86)/Graphviz2.38/bin"

Expected endmodule error while definig macro

I have defined a macro for gating gating assertion but while compiling, I am facing failure saying: endmodule expected at endproperty.
Code:
`define gating_check( _name, _clock, _data, txen) \
property _name ; \
#(posedge `TOP.``_clock``) disable iff (~`STIMULUS.RSTN_VEC_GEN) \
(~(txen) |-> ##[1:6] ( |`TOP.``_data`` == 0 ) ); \
endproperty \
``_name``_checker : assert property (_name) else $error("-E- property gating_check failed"); \
``_name``_cover : cover property (_name)
Pls help.
You just have extra space after the "\" in two lines - 4 and 5 , if you remove these trailing space the code should compile.
The "\" is used to escape the end of line but an extra space after the "\" will not do so. Hence now your macro has become a multi-lien statement generating the error. Because its a space character it difficult to observe :) .
Below is the code without the trailing space in line 4 and 5 .
`define gating_check( _name, _clock, _data, txen) \
property _name ; \
#(posedge `TOP.``_clock``) disable iff (~`STIMULUS.RSTN_VEC_GEN) \
(~(txen) |-> ##[1:6] ( |`TOP.``_data`` == 0 ) ); \
endproperty \
``_name``_checker : assert property (_name) else $error("-E- property gating_check failed"); \
``_name``_cover : cover property (_name)

TSC MSR and serialization

About the MSR IA32_TIME_STAMP_COUNTER (10h) :
Which rules of serialization does it follow ? rdtsc or rdtscp ? or other ?
If not serialized, should I provide a cpuid "barrier" before any math computations ?
-- Edit --
So far I have implemented two kinds of barriers : cpuid and fences.
With cpuid :
#define RDCOUNTER(_val, _cnt) \
asm volatile \
( \
"xorq %%rax, %%rax \n\t" \
"cpuid \n\t" \
"movq %1, %%rcx \n\t" \
"rdmsr \n\t" \
"push %%rax \n\t" \
"push %%rdx \n\t" \
"xorq %%rax, %%rax \n\t" \
"cpuid \n\t" \
"pop %%rdx \n\t" \
"pop %%rax \n\t" \
"shlq $32, %%rdx \n\t" \
"orq %%rdx, %%rax \n\t" \
"movq %%rax, %0" \
: "=m" (_val) \
: "i" (_cnt) \
: "%rax", "%rbx", "%rcx", "%rdx", "memory" \
)
With fence :
#define RDCOUNTER(_val, _cnt) \
asm volatile \
( \
"movq %1, %%rcx \n\t" \
"mfence \n\t" \
"rdmsr \n\t" \
"mfence \n\t" \
"shlq $32, %%rdx \n\t" \
"orq %%rdx, %%rax \n\t" \
"movq %%rax, %0" \
: "=m" (_val) \
: "i" (_cnt) \
: "%rax", "%rbx", "%rcx", "%rdx", "memory" \
)
Bellow part of my project is trying to estimate the processor external clock frequency (FSB or BCLK).
Algorithm allocates an array of a structured memory to read and measure deltas of the Time Stamp Counter.
This slab of memory is allocated to be resident in the processor cache.
A cpu affinity is made with the BSP, scheduler and interrupts are suspended the time of computation.
Several loops of the TSC reads are done to force cache residency; and the most occurrences of same result is declared as the best frequency.
What I expect is to get a constant frequency after several run.
Unfortunately, I still have variance whatever the barrier instruction is employed or not.
Results are pretty closed, at least 3 decimals past period, but never constant.
(this is tested on a Core 2 and Core i7)
DECLARE_COMPLETION(bclk_job_complete);
typedef struct {
unsigned long long V[2], D;
} TSC_STRUCT;
#define OCCURENCES 32
signed int Compute_Clock(void *arg)
{
CLOCK *clock=(CLOCK *) arg;
unsigned int ratio=clock->Q;
unsigned long long overhead=0;
struct kmem_cache *hardwareCache=kmem_cache_create(
"IntelClockCache",
OCCURENCES * sizeof(TSC_STRUCT), 0,
SLAB_HWCACHE_ALIGN, NULL);
TSC_STRUCT *TSC=kmem_cache_alloc(hardwareCache, GFP_KERNEL);
unsigned int loop=0, best=0, top=0;
// No preemption, no interrupt.
unsigned long flags;
preempt_disable();
raw_local_irq_save(flags);
// Warm-up
RDCOUNTER(TSC[loop].V[0], MSR_IA32_TSC);
RDCOUNTER(TSC[loop].V[1], MSR_IA32_TSC);
// Overhead
RDCOUNTER(TSC[loop].V[0], MSR_IA32_TSC);
RDCOUNTER(TSC[loop].V[1], MSR_IA32_TSC);
overhead=TSC[loop].V[1] - TSC[loop].V[0];
// Pick-up
for(loop=0; loop < OCCURENCES; loop++)
{
RDCOUNTER(TSC[loop].V[0], MSR_IA32_TSC);
udelay(100);
RDCOUNTER(TSC[loop].V[1], MSR_IA32_TSC);
}
// Restore interrupt and preemption.
raw_local_irq_restore(flags);
preempt_enable();
for(loop=0; loop < OCCURENCES; loop++)
TSC[loop].D=TSC[loop].V[1] - TSC[loop].V[0] - overhead;
for(loop=0; loop < OCCURENCES; loop++) {
unsigned int inner=0, count=0;
for(inner=loop; inner < OCCURENCES; inner++)
if(TSC[loop].D == TSC[inner].D)
count++;
if((count > top)
||((count == top) && (TSC[loop].D < TSC[best].D))) {
top=count;
best=loop;
}
/* printk("%3u x D[%02u]=%llu\t%llu - %llu\n",
count, loop, TSC[loop].D, TSC[loop].V[1], TSC[loop].V[0]); */
}
printk("Overhead=%llu\tBest=%llu\n", overhead, TSC[best].D);
clock->Q=TSC[best].D / (ratio * PRECISION);
clock->R=TSC[best].D % (ratio * PRECISION);
kmem_cache_free(hardwareCache, TSC);
kmem_cache_destroy(hardwareCache);
complete_and_exit(&bclk_job_complete, 0);
}