We have found that with our memcache some keys tend to be lost. To debug, I am using the command stats cachedump <slab> <limit>
The output is something like this :
ITEM key-stuff-123-mlgtr-tmura [58 b; 1256946310 s]
ITEM key-stuff-123-mlgtr-isuca [58 b; 1256946310 s]
ITEM key-stuff-123-mlgtr-arpan [58 b; 1256946310 s]
ITEM key-stuff-123-mlgtr-nanhai [59 b; 1256946252 s]
ITEM key-stuff-123-mlgtr-naka3 [58 b; 1256946250 s]
ITEM key-stuff-123-mlgtr-erlang [59 b; 1256946250 s]
ITEM key-stuff-123-mlgtr-junkma [59 b; 1256946250 s]
ITEM key-stuff-123-mlgtr-wilfue [59 b; 1256946250 s]
ITEM key-stuff-123-mlgtr-quinte [59 b; 1256946250 s]
ITEM key-stuff-123-mlgtr-yanbe [58 b; 1256946250 s]
I get that 58 b is the size; but what would be 1256946250 s? The expiration in seconds? That seems kind of high (55 years)! So maybe our problem lies here... or maybe I misunderstood something.
Thanks!
It's the expiration time, as a unix timestamp.
So, item with '1256946250' will expire 'Sat Oct 31 01:44:10 2009'
Those are unix style timestamps. You can go here to convert them to a human readable date time. Basically, it is the number of seconds since Jan 01 1970
Related
I have this 4 bit ring counter that I'm trying to make, and I feel like I'm so close, but I can't figure out how to make one input depend on the previous state's output. Here's what I have:
`default_nettype none
// Empty top module
module top (
// I/O ports
input logic hz100, reset,
input logic [20:0] pb,
output logic [7:0] left, right
);
// Your code goes here...
q[3:0];
assign q[3:0] = right[3:0];
hc74_set setFF(.c(pb[0]), .d(pb[1]), .q(right[0]), .sn(pb[16]));
hc74_reset resetFF1(.c(pb[0]), .d(pb[1]), .q0(right[1]), .rn(pb[16]));
hc74_reset resetFF2(.c(pb[0]), .d(pb[1]), .q1(right[2]), .rn(pb[16]));
hc74_reset resetFF3(.c(pb[0]), .d(pb[1]), .q2(right[3]), .rn(pb[16]));
endmodule
// Add more modules down here...
// This is a single D flip-flop with an active-low asynchronous set (preset).
// It has no asynchronous reset because the simulator does not allow it.
// Other than the lack of a reset, it is half of a 74HC74 chip.
module hc74_set(input logic d, c, sn,
output logic q, qn);
assign qn = ~q;
always_ff #(posedge c, negedge sn)
if (sn == 1'b0)
q <= 1'b1;
else
q <= d;
endmodule
// This is a single D flip-flop with an active-low asynchronous reset (clear).
// It has no asynchronous set because the simulator does not allow it.
// Other than the lack of a set, it is half of a 74HC74 chip.
module hc74_reset(input logic d, c, rn,
output logic q, qn);
assign qn = ~q;
always_ff #(posedge c, negedge rn)
if (rn == 1'b0)
q <= 1'b0;
else
q <= d;
endmodule
This is on an FPGA simulator, which is why there are a few things like pb (these are push buttons) and left, right outputs which are sets of 8 LEDs each.
Let's first make sure we are on the same page
Based on wikipedia description of a ring counter
This could be implemented as follows:
module top (
// I/O ports
input logic reset_n,
input logic clk,
output logic [3:0] ring
);
// Your code goes here...
always #(posedge clk or negedge reset_n) begin
if(~reset_n) begin
ring = 4'b0001;
end
else begin
ring[0] <= ring[3];
ring[1] <= ring[0];
ring[2] <= ring[1];
ring[3] <= ring[2];
end
end
endmodule
The output ring is a 4-bit one hot vector, reset_n = 0 makes ring = 0001 every clock with reset_n = 1 rolls the ring to the right, [0001, 0010, 0100, 1000, 0001, ...].
But you want to use instances of the flops you defined. Notice that in an assignment a <= b, a is the output of the flop (q port), and b is the input of the flop (d port).
module top (
// I/O ports
input logic reset_n,
input logic clk,
output logic [3:0] ring
);
// Your code goes here...
hc74_set setFF(.c(clk), .d(ring[3]), .q(ring[0]), .sn(reset_n));
hc74_reset resetFF1(.c(clk), .d(ring[0]), .q0(ring[1]), .rn(reset_n));
hc74_reset resetFF2(.c(clk), .d(ring[1]), .q1(ring[2]), .rn(reset_n));
hc74_reset resetFF3(.c(clk), .d(ring[2]), .q2(ring[3]), .rn(reset_n));
endmodule
You have to connect the ports accordingly, I just used clk for the clock and reset_n for the negated reset signal.
Can s_clk be passed as argument to xyz task in below code?
module test(input logic m_clk, output [1:0] logic s_clk);
...
xyz (m_clk,s_clk);//assuming m_clks and s_clks are generated from top
...
task automatic xyz (ref logic clk1, ref [1:0] logic clk2);
...
endtask
endmodule
I have read your problem, first of all you have typo mistake
module test(input logic m_clk, output [1:0] logic s_clk);
task automatic xyz (ref logic clk1, ref [1:0] logic clk2);
instead of this you have to write
module test(input logic m_clk, output logic [1:0] s_clk);
task automatic xyz (ref logic clk1, ref logic [1:0] clk2);
For better understanding I have also share one demo code for packed arrays can be passed by reference to the task in systemverilog.
Here is code :
program main();
bit [31:0] a = 25;
initial
begin
#10 a = 7;
#10 a = 20;
#10 a = 3;
#10 $finish;
end
task pass_by_val(int i);
$monitor("===============================================%d",i);
forever
#a $display("pass_by_val: I is %0d",i);
endtask
task pass_by_ref(ref bit [31:0]i);
forever
begin
#a $display("pass_by_ref: I is %0d",i[0]);
$display("This is pass_by value a ====== %d \n a[0] ====== %0d ",a,a[0]);
end
endtask
initial
begin
pass_by_val(a);
end
initial
pass_by_ref(a);
endprogram
By running this example you can observe that packed arrays can be passed by reference to the task in systemverilog and its value is also reflected to it.
pass_by_val task will register the value of the variables
only once at the time when task is called. Subsequently when the variable changes its value, pass_by_val task cannot see the newer values. On the other hand, 'ref' variables in a task are registered whenever its value changes. As a result, when the variable 'a' value changes, the pass_by_ref task can register and display the value correctly.
I simulated Ashutosh Rawal's code and the output display is given below:
=============================================== 25
pass_by_val: I is 25
pass_by_ref: I is 1
This is pass_by value a ====== 7
a[0] ====== 1
pass_by_val: I is 25
pass_by_ref: I is 0
This is pass_by value a ====== 20
a[0] ====== 0
pass_by_val: I is 25
pass_by_ref: I is 1
This is pass_by value a ====== 3
a[0] ====== 1
$finish called from file "testbench.sv", line 13.
$finish at simulation time 40
V C S S i m u l a t i o n R e p o r t
JVM crashes unexpectedly from time to time in our servers with SIGSEGV. We are using JNI to call some C functions which eventually use ECPG to talk to postgres db.
Here is a stack trace for reference:
Stack: [0xa895e000,0xa89af000], sp=0xa89ab550, free space=309k
Native frames: (J=compiled Java code, j=interpreted, Vv=VM code, C=native code)
C [libpq.so.5+0x1a42c] resetPQExpBuffer+0x2c
C [libpq.so.5+0x1a46f] printfPQExpBuffer+0x1f
C [libpq.so.5+0x10b1a] PQgetResult+0xea
C [libpq.so.5+0x10c97]
C [libpq.so.5+0x110e7] PQexec+0x27
C [libecpg.so.6+0x506f] ECPGdo+0xc5f
C [libvcswsilib.so+0x9b914] get_codes_info+0x4eb
C [libvcswsilib.so+0x4b4c8] getCodes(CConference*, CUser const&)+0xc8
C [libvcswsilib.so+0x4d06d] CConf::GetFromDatabase(CUser const&, std::string const&)+0x203
C [libvcswsilib.so+0x4ce0f] CConf::GetFromDatabaseViaEitherCode(CUser const&, std::string const&)+0xd7
C [libvcswsilib.so+0x3acac] getCommon(CUser&, std::string const&, std::string&)+0x45
C [libvcswsilib.so+0x3b56e] getCred(std::string const&, std::string&)+0x107
C [libvcswsilib.so+0x376fa] WebServiceImpl_getCredJNI+0x78
j WebServiceImpl.getCredJNI(Ljava/lang/String;)Ljava/lang/String;+0
j WebServiceImpl.getInfo(Ljava/net/InetSocketAddress;Lcom/Lis tener;Ljava/util/HashMap;)Ljava/lang/String;+51
j MessageProcessor.processInfo(Lcom/wss/MessageProcessor$MessagePacket;)V+47
j MessageProcessor.processMessage(Lcom/wss/Manager$MessagePacket;Ljava/lang/String;)V+79
J 388% C2 Manager.run()V (257 bytes) # 0xf4737b9c [0xf47370c0+0xadc]
j java.lang.Thread.run()V+11
v ~StubRoutines::call_stub
V [libjvm.so+0x459d54]
V [libjvm.so+0x61b129]
V [libjvm.so+0x45923a]
V [libjvm.so+0x45936b]
V [libjvm.so+0x4a4ffc]
V [libjvm.so+0x73b040]
V [libjvm.so+0x73b339]
V [libjvm.so+0x622689]
C [libpthread.so.0+0x6b39] start_thread+0xc9
We have scanned through the native and Java code and didn't find anything which might be leading to this issue. Don't have much idea on the working of ECPG or postgres.
Any kind of help/idea for debugging the issue will be much appreciated.
I am newbie with Perl. I have an assignment to transpose rows into columns of a huge data.
customers goods transportation
---------- ----- --------------
A, B, C, D rice truck
E, G, D corn train
............. ..... .........
T, H, K, M, N wheat air cargo
And I would like to have an output look like:
customers goods transportation
---------- ----- --------------
A rice truck
B rice truck
C rice truck
D rice truck
............. ..... .........
N wheat air cargo
Could anyone help. Thank you very much.
Most probably you have come across the map function, study how it works and how you construct rows or columns and you will get it, good luck! :)
Thank you all. After few hours trying I could figure out how to do my assignment.
It needs some simple steps of manually intervention for the input and output,
i.e. add an , at the end of the first column of the input and remove \ in
the second column of the output using Excel.
It is time to submit the output. I appreciate if someone has a better Perl
code to solve it.
#!/usr/bin/perl
my #records;
while (<DATA>) {
chomp;
my #columns = split ", ", $_;
push #records, \#columns;
}
foreach my $record (#records) {
foreach my $column (#{$record}) {
if (\$column != \$$record[-1]) {
print "$column\t \\$$record[-1]\n";
}
}
}
__DATA__
A, B, C, D, Rice Truck
E, G, D, Corn Train
T, H, K, M, N, Wheat Air cargo
__OUTPUT__
A \ Rice Truck
B \ Rice Truck
C \ Rice Truck
D \ Rice Truck
E \ Corn Train
G \ Corn Train
D \ Corn Train
T \ Wheat Air cargo
H \ Wheat Air cargo
K \ Wheat Air cargo
M \ Wheat Air cargo
N \ Wheat Air cargo
It's a long time since I looked at perl, but is this perl mod any good?
Data::Pivot
Is there an R timer or stopwatch function similar to MATLAB's tic/toc?
There are plenty of profiling tools in R, as Dirk mentioned. If you want the simplicity of tic/toc, then you can do it in R too.
EDIT: I've cannibalised the garbage collection functionality from the MATLAB package, and tic now lets you choose whether you are interested in total elapsed time or just the user time.
tic <- function(gcFirst = TRUE, type=c("elapsed", "user.self", "sys.self"))
{
type <- match.arg(type)
assign(".type", type, envir=baseenv())
if(gcFirst) gc(FALSE)
tic <- proc.time()[type]
assign(".tic", tic, envir=baseenv())
invisible(tic)
}
toc <- function()
{
type <- get(".type", envir=baseenv())
toc <- proc.time()[type]
tic <- get(".tic", envir=baseenv())
print(toc - tic)
invisible(toc)
}
Usage is, e.g., tic(); invisible(qr(matrix(runif(1e6), nrow=1e3))); toc()
There is a MATLAB emulation package matlab on CRAN. It has implementations of tic and toc (but they look very similar to the functions in Richie Cottons answer; "elapsed" is used instead of "user.self" in proc.time())
> tic
function (gcFirst = FALSE)
{
if (gcFirst == TRUE) {
gc(verbose = FALSE)
}
assign("savedTime", proc.time()[3], envir = .MatlabNamespaceEnv)
invisible()
}
<environment: namespace:matlab>
> toc
function (echo = TRUE)
{
prevTime <- get("savedTime", envir = .MatlabNamespaceEnv)
diffTimeSecs <- proc.time()[3] - prevTime
if (echo) {
cat(sprintf("elapsed time is %f seconds", diffTimeSecs),
"\n")
return(invisible())
}
else {
return(diffTimeSecs)
}
}
<environment: namespace:matlab>
A very simple equivalence with tic and toc that you could have:
tic=proc.time()[3]
...code...
toc=proc.time()[3] - tic
Where the [3] is because we are interested in the third element in the vector returned by proc.time(), which is elapsed time.
Direct equivalents of tic and toc do not exist.
Please see help(system.time) as well as the R Extensions manual about profiling. Discussions of profiling and profiling tools is also in the 'Intro to HPC with R' slides referenced on the High Performance Computing with R taskview
A Closure Approach
A very clean and simple way to do this is by using a closure (which just means having a function within a function):
tic <- function () {
now <- proc.time()
function () {
proc.time() - now
}
}
You start the timer like so:
toc <- tic()
And then you get the time back like this:
toc()
Which outputs a named vector that gets printed like so:
user system elapsed
0.008 0.004 2.055
Even with the simplicity of this version you also get all the functionality of the Matlab and Richie Cotton's versions plus the added feature of being able to run multiple timers:
toc1 <- tic()
toc2 <- tic()
There is a relatively new package tictoc that replicates the features exactly as you would use them in Matlab.
http://cran.r-project.org/web/packages/tictoc/index.html
## Basic use case
tic()
print("Do something...")
Sys.sleep(1)
toc()
# 1.034 sec elapsed
As of the date 2015-03-25,
and possibly earlier,
the pracma
package contains the functions tic() and toc().
Example:
> library(pracma)
> tic()
> for(i in 1:10000) mad(runif(10000)) # kill time
> toc()
elapsed time is 18.610000 seconds
No, but here is a one line solution.
time.it<-function(f) { a<-proc.time(); out<-f(); print(proc.time()-a); out }
And an example for usage:
result<-time.it(function(){ A<-matrix(runif(5000^2),nrow=5000); b<-runif(5000); solve(A,b) } )
user system elapsed
12.788 12.268 8.623
Otherwise, microbenchmark is my favorite in terms of packages.
Just for completeness: you can actually 'simulate' tic
and toc in R, so that you can write
tic
## do something
toc
without parentheses. The trick is to abuse the print
function, as demonstrated in Fun: tic and toc in R:
tic <- 1
class(tic) <- "tic"
toc <- 1
class(toc) <- "toc"
print.tic <- function(x, ...) {
if (!exists("proc.time"))
stop("cannot measure time")
gc(FALSE)
assign(".temp.tictime", proc.time(), envir = .GlobalEnv)
}
print.toc <- function(x,...) {
if (!exists(".temp.tictime", envir = .GlobalEnv))
stop("did you tic?")
time <- get(".temp.tictime", envir = .GlobalEnv)
rm(".temp.tictime", envir = .GlobalEnv)
print(res <- structure(proc.time() - time,
class = "proc_time"), ...)
invisible(res)
}
So typing
tic
Sys.sleep(2)
toc
should results in something like this:
user system elapsed
0.000 0.000 2.002
As I said, it's a trick; system.time, Rprof and
packages such as rbenchmark are the way to measure
computing time in R.
install.packages("tictoc")
library(tictoc)
# Timing nested code.
# The string provided in the call to tic() becomes a prefix to the output of toc()
tic("outer")
Sys.sleep(1)
tic("middle")
Sys.sleep(2)
tic("inner")
Sys.sleep(3)
toc() # inner
# inner: 3.004 sec elapsed
toc() # middle
# middle: 5.008 sec elapsed
toc() # outer
# outer: 6.016 sec elapsed
The tictoc package implements the functionality described by previous answers - thank you for inspiration! The package also adds nested timing, collecting the timings in user-defined variables, custom messages and callbacks.