What advantage did we have in using a wider external data bus, say 64 bit in first Pentium produced in 1993, when the size of the internal data bus or registers was 32 bit only?
General purpose registers may be only be 32 bits, but there are wider registers, e.g. floating point, MMX, SSE, which may be 64 bits or more.
Note also that whole cache lines are read/written from/to memory.
From Chapter 23 of 'The x86 PC Assembly language, Design and Interface' by Muhammad Ali Mazidi:
In the pentium, the external data buses are 64 bit, which will bring twice as much code and data into the CPU as the 486. However, just like the 386 and 486, Pentium registers are 32 bit. Bringing in twice as much as information can work only if there are two execution units inside the processor, and this is exactly what Intel has done.
Related
Does a 64 bit run-time run faster than a 32 bit? Was our childhood a lie?
Backstory:
A runtime I really like has been updated to 64 bit. As a programmer, the only thing I could think of was that meant that you could create larger numbers and access more memory.
But growing up the newest consoles went from 8 bit, to 16 bit, then 32 bit and you won't guess what's next, 64 bit. So everyone knew 16 bit was better in every way, including speed, than 8 bit.
So when my favorite runtime says it's upgraded to 64 bit does it mean it's faster than the 32 bit? It's upgraded for Mac OS X and will be upgraded to 64 bit for Windows as well.
Also, it looks like Firefox just went 64 bit.
The processor word size (32 or 64) is somewhat independent of the the speed. Generally 64-bit processors are newer than those supporting only 32-bits, so they are inherently faster. However, manipulating more data, larger addresses is inherently slower than manipulating smaller data (shorter addresses).
Let's say that you have a library that does image processing (e.g., read/write JPEG files) in which you need to do 64-bit scaled integers (at 32-bits, you get serious rounding errors in JPEG). The 64-bit processor can add a 64-bit scale integer in one instruction. A 32-bit processor would take 3 or more instructions to do the same (inherently slower).
64 bits means access to more memory (if you use a CAD program you know what that means); not more speed. But, because 64-bit processors tend to be newer and faster, you generally get more speed; but not because of 64-bits.
Here is an answer from a low level developer, x64 can be very optimized because it has 8 additional 128 bit Multimedia XMM Registers, All 32 Bit registers are extended to 64 Bit, and an additional 8 General Purpose registers R8-R15. This all can be used to minimize memory access, computations, and copying large buffers which are the main slowdown for a CPU, programs in x64 already know there is SSE & SSE2 So they can benefit from these extensions without checking for them or creating double the functions. (there is also 256Bit AVX/512Bit AVX512).
The main thing about why they are called 64 bit is because these processors provide a 64 Bit Flat Address space when you can use 48 Bit Paging (256 TB) or (if supported) 57 Bit Paging (2^57 Bytes).
I have tried to get a grasp of what "word" means and I have looked in the wiki and the definition is vague. So my question is what is "word size"? Is it the length of the data bus, address bus?
"Word size" refers to the number of bits processed by a computer's CPU in one go (these days, typically 32 bits or 64 bits). Data bus size, instruction size, address size are usually multiples of the word size.
Just to confuse matters, for backwards compatibility, Microsoft Windows API defines a WORD as being 16 bits, a DWORD as 32 bits and a QWORD as 64 bits, regardless of the processor.
One answer is -- not as much as it used to. Way back when, computers could only load/store full "words" of memory, which would be 16/24/32/36/48 bits each (depending on the particular machine). One would have to carefully structure their program design around the word size of the target machine.
But any more computers can access individual bytes or can access strings of data dozens of bytes long, with one relatively seamless operation. Much more significant than the technical word size is the memory buss width, which determines how many bytes can be transferred between CPU and memory in one memory "cycle".
So "word size" is somewhat meaningless, and (as another answer suggests) companies like Microsoft will often define it in an arbitrary manner, with no real relationship to anything.
Consider the following:
CPU (processor), RAM (main memory), I/O devices (mouse, keyboard, printer), Bus (data transfer component).
How would you like these computer parts to communicate and transfer data?
you definitely need a fixed size of bits to be considered a single unit of data.
For that, Computer scientists agreed to standardize this unit to be 32 bits or 64 bits (depending on the manufacturer choice).
They gave this unit a name and called it a Word.
So a Word is nothing but a unit of data (bunch of bits (signal charges of zeros and ones)) that moves around from a computer component to another.
For instance buses are built with 32 bits (4 bytes) and some with 64 bits (8 bytes). Likewise with the CPU (hardware) and operating systems (software) are built with either 32 bits or 64 bits.
It just happened to be the standard unit named Word and sized 32 bits or 64 bits.
Ps: Word is one of the many data size units that move around inside the computer, different computer components use different sizes to transport data (signals charges that represent zeros and ones), for instance RAM can use size of 64 bits while Buses can use 32 bits. Hardware designers design the architecture of components taking into account these size differences to either implement Word size of 32 bits on only CPU but 64 bits on RAM, or implement the same size on all components, ...etc. Word size used to be 8 bits (1 byte), but nowadays the most comment unit size is 64 bits on most computer components such as CPU or RAM, or Bus, ...etc.
Word size means the no. of bits of data processed by the microprocessor as a unit.
Word is set of bits acts as a single unit of data processed by microprocessor. However, it can be any set value, common values included: 16, 18, 24, 32, 36, 40, 48, and 64.
Analogy:
In English language, word is a single distinct meaningful element of speech or writing, used with others to form a sentence.
In a book I read the following:
32-bit processors have 2^32 possible addresses, while current 64-bit processors have a 48-bit address space
My expectation was that if it's a 64-bit processor, the address space should also be 2^64.
So I was wondering what is the reason for this limitation?
Because that's all that's needed. 48 bits give you an address space of 256 terabyte. That's a lot. You're not going to see a system which needs more than that any time soon.
So CPU manufacturers took a shortcut. They use an instruction set which allows a full 64-bit address space, but current CPUs just only use the lower 48 bits. The alternative was wasting transistors on handling a bigger address space which wasn't going to be needed for many years.
So once we get near the 48-bit limit, it's just a matter of releasing CPUs that handle the full address space, but it won't require any changes to the instruction set, and it won't break compatibility.
Any answer referring to the bus size and physical memory is slightly mistaken, since OP's question was about virtual address space not physical address space. For example the supposedly analogous limit on some 386's was a limit on the physical memory they could use, not the virtual address space, which was always a full 32 bits. In principle you could use a full 64 bits of virtual address space even with only a few MB of physical memory; of course you could do so by swapping, or for specialized tasks where you want to map the same page at most addresses (e.g. certain sparse-data operations).
I think the real answer is that AMD was just being cheap and hoped nobody would care for now, but I don't have references to cite.
Read the limitations section of the wikipedia article:
A PC cannot contain 4 petabytes of memory (due to the size of current memory chips if nothing else) but AMD envisioned large servers, shared memory clusters, and other uses of physical address space that might approach this in the foreseeable future, and the 52 bit physical address provides ample room for expansion while not incurring the cost of implementing 64-bit physical addresses
That is, there's no point implementing full 64 bit addressing at this point, because we can't build a system that could utilize such an address space in full - so we pick something that's practical for today's (and tomorrow's) systems.
The internal native register/operation width does not need to be reflected in the external address bus width.
Say you have a 64 bit processor which only needs to access 1 megabyte of RAM. A 20 bit address bus is all that is required. Why bother with the cost and hardware complexity of all the extra pins that you won't use?
The Motorola 68000 was like this; 32 bit internally, but with a 23 bit address bus (and a 16 bit data bus). The CPU could access 16 megabytes of RAM, and to load the native data type (32 bits) took two memory accesses (each bearing 16 bits of data).
There is a more severe reason than just saving transistors in the CPU address path: if you increase the size of the address space you need to increase the page size, increase the size of the page tables, or have a deeper page table structure (that is more levels of translation tables). All of these things increase the cost of a TLB miss, which hurts performance.
From my point of view, this is result from the page size.Each page at most contains 4096/8 =512 entries of page table. And 2^9 =512. So 9 * 4 + 12=48.
Many people have this misconception. But I am promising to you if you read this carefully, after reading this all your misconceptions will be cleart.
To say a processor 32 bit or 64 bit doesn't signify it should have 32 bit address bus or 64 bit address bus respectively!...I repeat it DOESN'T!!
32 bit processor means it has 32 bit ALU (Arithmetic and Logic Unit)...that means it can operate on 32 bit binary operand (or simply saying a binary number having 32 digits) and similarly 64 bit processor can operate on 64 bit binary operand. So weather a processor 32 bit or 64 bit DOESN'T signify the maximum amount of memory can be installed. They just show how large the operand can be...(for analogy you can think of a 10-digit calculator can calculate results upto 10 digits...it cannot give us 11 digits or any other bigger results... although it is in decimal but I am telling this analogy for simplicity)...but what you are saying is address space that is the maximum directly interfaceable size of memory (RAM). The RAM's maximum possible size is determined by the size of the address bus and it is not the size of the data bus or even ALU on which the processor's size is defined (32/64 bit). Yes if a processor has 32 bit "Address bus" then it is able to address 2^32 byte=4GB of RAM (or for 64 bit it will be 2^64)...but saying a processor 32 bit or 64 bit has nothing relevance to this address space (address space=how far it can access to the memory or the maximum size of RAM) and it is only depended on the size of its ALU. Of course data bus and address bus may be of same sized and then it may seem that 32 bit processor means it will access 2^32 byte or 4 GB memory...but it is a coincidence only and it won't be the same for all....for example intel 8086 is a 16 bit processor (as it has 16 bit ALU) so as your saying it should have accessed to 2^16 byte=64 KB of memory but it is not true. It can access upto 1 MB of memory for having 20 bit address bus....You can google if you have any doubts:)
I think I have made my point clear.Now coming to your question...as 64 bit processor doesn't mean that it must have 64 bit address bus so there is nohing wrong of having a 48 bit address bus in a 64 bit processor...they kept the address space smaller to make the design and fabrication cheap....as nobody gonna use such a big memory (2^64 byte)...where 2^48 byte is more than enough nowadays.
To answer the original question: There was no need to add more than 48 Bits of PA.
Servers need the maximum amount of memory, so let's try to dig deeper.
1) The largest (commonly used) server configuration is an 8 Socket system. An 8S system is nothing but 8 Server CPU's connected by a high speed coherent interconnect (or simply, a high speed "bus") to form a single node. There are larger clusters out there but they are few and far between, we are talking commonly used configurations here. Note that in the real world usages, 2 Socket system is one of the most commonly used servers, and 8S is typically considered very high end.
2) The main types of memory used by servers are byte addressable regular DRAM memory (eg DDR3/DDR4 memory), Memory Mapped IO - MMIO (such as memory used by an add-in card), as well as Configuration Space used to configure the devices that are present in the system. The first type of memory is the one that are usually the biggest (and hence need the biggest number of address bits). Some high end servers use a large amount of MMIO as well depending on what the actual configuration of the system is.
3) Assume each server CPU can house 16 DDR4 DIMMs in each slot. With a maximum size DDR4 DIMM of 256GB. (Depending on the version of server, this number of possible DIMMs per socket is actually less than 16 DIMMs, but continue reading for the sake of the example).
So each socket can theoretically have 16*256GB=4096GB = 4 TB.
For our example 8S system, the DRAM size can be a maximum of 4*8= 32 TB. This means that
the max number of bits needed to address this DRAM space is 45 (=log2 32TB/log2 2).
We wont go into the details of the other types of memory (MMIO, MMCFG etc), but the point here is that the most "demanding" type of memory for an 8 Socket system with the largest types of DDR4 DIMMs available today (256 GB DIMMs) use only 45 bits.
For an OS that supports 48 bits (WS16 for example), there are (48-45=) 3 remaining bits.
Which means that if we used the lower 45 bits solely for 32TB of DRAM, we still have 2^3 times of addressable memory which can be used for MMIO/MMCFG for a total of 256 TB of addressable space.
So, to summarize:
1) 48 bits of Physical address is plenty of bits to support the largest systems of today that are "fully loaded" with copious amounts of DDR4 and also plenty of other IO devices that demand MMIO space. 256TB to be exact.
Note that this 256TB address space (=48bits of physical address) does NOT include any disk drives like SATA drives because they are NOT part of the address map, they only include the memory that is byte-addressable, and is exposed to the OS.
2) CPU hardware may choose to implement 46, 48 or > 48 bits depending on the generation of the server. But another important factor is how many bits does the OS recognize.
Today, WS16 supports 48 bit Physical addresses (=256 TB).
What this means to the user is, even though one has a large, ultra modern server CPU that can support >48 bits of addressing, if you run an OS that only supports 48 bits of PA, then you can only take advantage of 256 TB.
3) All in all, there are two main factors to take advantage of higher number of address bits (= more memory capacity).
a) How many bits does your CPU HW support? (This can be determined by CPUID instruction in Intel CPUs).
b) What OS version are you running and how many bits of PA does it recognize/support.
The min of (a,b) will ultimately determine the amount of addressable space your system can take advantage of.
I have written this response without looking into the other responses in detail. Also, I have not delved in detail into the nuances of MMIO, MMCFG and the entirety of the address map construction. But I do hope this helps.
Thanks,
Anand K Enamandram,
Server Platform Architect
Intel Corporation
It's not true that only the low-order 48 bits of a 64 bit VA are used, at least with Intel 64. The upper 16 bits are used, sort of, kind of.
Section 3.3.7.1 Canonical Addressing in the Intel® 64 and IA-32 Architectures Software Developer’s Manual says:
a canonical address must have bits 63 through 48 set to zeros or ones (depending on whether bit 47 is a zero or one)
So bits 47 thru 63 form a super-bit, either all 1 or all 0. If an address isn't in canonical form, the implementation should fault.
On AArch64, this is different. According to the ARMv8 Instruction Set Overview, it's a 49-bit VA.
The AArch64 memory translation system supports a 49-bit virtual address (48 bits per translation table). Virtual addresses are sign- extended from 49 bits, and stored within a 64-bit pointer. Optionally, under control of a system register, the most significant 8 bits of a 64-bit pointer may hold a “tag” which will be ignored when used as a load/store address or the target of an indirect branch
A CPU is considered "N-bits" mainly upon its data-bus size, and upon big part of it's entities (internal architecture): Registers, Accumulators, Arithmetic-Logic-Unit (ALU), Instruction Set, etc. For example: The good old Motorola 6800 (or Intel 8050) CPU is a 8-bits CPU. It has a 8-bits data-bus, 8-bits internal architecture, & a 16-bits address-bus.
Although N-bits CPU may have some other than N-size entities. For example the impovments in the 6809 over the 6800 (both of them are 8-bits CPU with a 8-bits data-bus). Among the significant enhancements introduced in the 6809 were the use of two 8-bit accumulators (A and B, which could be combined into a single 16-bit register, D), two 16-bit index registers (X, Y) and two 16-bit stack pointers.
I have read that the microprocessor consists of several components, each having same/different "sizes". But what really confuses me is what determines the stated size of a microprocessor as 16-bit, 32-bit or 64-bit...
Is it:
the the ALU's capacity?
the size of the data bus?
the size of the address bus?
the "least common denominator" of the above?
or some other factor that I hitherto don't know about?
Generally the bit-size of a processor is the size of its general purpose registers. this often corresponds to the size of the memory bus and possibly the address bus, but doesn't necessarily.
For example, Intel sold a version of the 386 chip called the 386SX (http://en.wikipedia.org/wiki/Intel_80386#The_i386SX_variant) that internally was a 386 with 32-bit registers, but only has a 16 bit data bus. I think that most people would consider the chip to still be a 32-bit processor instead of a 16 bit processor.
I think I'll have a go. Traditionally I think that "size" meant the width (number of bits) in the register set. On "my" first computer the DEC PDP-8/E the single register available - the accumulator - was 12 bits wide and it was a 12-bit computer, on the PDP-11 the registers were 16 bits wide and it was a 16-bit computer. IBM 370 and VAX had 32-bit registers and were 32-bit computers.
Starting with the 80386 things became difficult. Depending on operating mode it could present itself to be a real mode 8086, a protected mode (PM) 80286 or a PM 80386. With the 64-bit processors using AMD64 or x86-64 you have all of the above and also 64-bit PM. So what are they? It should depend on the basic operating mode of the OS that's running on it. Windows NT 2000, Windows XP-32, Vista-32 7-32 make the processor 32-bit. OS with "64" in them make the processor 64 bit.
As to buses and stuff. There are two physical buses on x86-processors address+data and two logical buses memory+i/o. Special pins on the processor determine if the operation is memory or i/o, read or write and so on. On the 8086/8088 the data and address buses shared the same pins A0-A15 with D0-D15/A0-A7 with D0-D7 with bits A16-A19/A8-A19 being strictly address. On the 80286 they were separate, not sure about the 80186/80188. On the 80286 there were 24 address and 16 data lines. On the 80386 and 80486 there were 32 each for address and data. The 80386SX had the same external configuration as the 80286.
After this buses get complicated. The processors run so fast internally that they are more or less constantly waiting for their caches which in turn are more or less constantly waiting on external RAM. To satisfy the caches' insatiable hunger for data external memory began delivering it in 64 bit wide chunks starting with the Pentium and Pentium MMX that are both 32 bit processors with 32 address lines but with 64 data lines.
With later processors the number of address lines were increased to 36 allowing a total addressable external memory of 64 GB. The processors remained 32-bit internally.
On multi-core processors the hunger for data is even more pronounced so they may have several sets of address and data buses to faciltiate data being crammed into the processor. Desktop processors may have two or three and server processors three to four. I'm not sure but I believe some have switched to 128 bit wide data buses.
For modern 64-bit processors it is not feasible to also have 64 address lines since that would allow memory up to 16 billion Gigabytes which is not possible today. Some motherboards allow 128 GB which means that the processor needs at least 37 address lines.
As you can see address and data buses are no longer really usable to determine processor size. They actually haven't for the last 25 (80386 modes) years.
In C the int type is supposed to be equivalent to the register width. On AMD64 it isn't because there just isn't that great a need for 64 bit ints: 32 bit ints do just nicely in most cases. The width of a pointer in C on AMD64 is 64 bits though.
Generally this refers to the amount of the memory (2^n) bytes that is addressable by the CPU. Usually it's the same as data bus, but the hardware may do multiple accesss to retrieve that amount so is not 100% guaranteed. Sometimes it also corresponds to CPU register size, however it too can be different.
While reading one Freescale processor manual I stuck somewhere, which specifies that it is a 32-bit processor.
May I know the exact meaning and logic behind that?
Update:
Does it specify its ALU width or its address width or its register width specifically or all of them together is N-bit each.
Update:
Hope you have heard of Freescale processors. I just came across their site which describes one of their latest Starcore-based processor known as SC3850 as a 16-bit processor. As far as I know, it has 32 bit program counters, including ALU, and 40-bit register width and 2x64 bit address bus width. Also the SC3850 can handle SIMD(2) instructions which are of 32 bit or 64 bit.
For more details please go through this link
One of the major reasons you would care about the register width of the processor is performance. Generally doubling the number of bits doubles the rate at which a processor can move data around, and compute. This is why we're not all using 8 bit processors.
The other major reason is address space. A 16 bit program counter limits you to 64k of address space, and a 32 bit counter limits you to 4 gigabytes. The new 64 bit processors make it possible, if all the address lines are present, to support 17,179,869,184 gigabytes of memory.
Firstly i dont have a definitive answer but i would guess that 8 being a power of 2, is an important factor. Being a power of 2 also means that certain optimisations may be performed by dividing the 8 bits into groups which also means lookup tables can be used for certain operations. 8 bits in the past was also the perfect size when dealing wiht plain old ascii characters. I can imagine that using 5 bit bytes and encoding a string of ascii characters across memory would be a pain.
Please check out the Wikipedia entry on 32-bit processors, from the entry:
In computer architecture, 32-bit
integers, memory addresses, or other
data units are those that are at most
32 bits (4 octets) wide. Also, 32-bit
CPU and ALU architectures are those
that are based on registers, address
buses, or data buses of that size.
32-bit is also a term given to a
generation of computers in which
32-bit processors were the norm.
Read and understand the article - then the answer for N will be obvious.