I encountered a problem when trying to connect a component to two output ports of parent hierarchy in VHDL. Since the physical connection can be done only via "port map" statement, there is no way to connect local signal to more than one output port. Here is an example:
The description of the above circuit should be smth. like this:
entity HIER is
port (
IN1 : in bit;
OUT1, OUT2 : out bit);
end hier;
architecture HIER_IMPL of HIER is
component BUF is
port (a : in bit; o : out bit);
end component;
begin
BUF1 : BUF port map (a => IN1, o => OUT1, o => OUT2);
end HIER_IMPL;
However, double assignment of output port "o" to both OUT1 and OUT2 won't work as it is prohibited in VHDL.
Is there a reason why you cannot create an internal signal and use that signal to drive the two output ports like this?
entity HIER is
port (
IN1 : in bit;
OUT1, OUT2 : out bit);
end hier;
architecture HIER_IMPL of HIER is
signal temp : bit;
component BUF is
port (a : in bit; o : out bit);
end component;
begin
BUF1 : BUF port map (a => IN1, o => temp);
OUT1 <= temp;
OUT2 <= temp;
end HIER_IMPL;
If this is not possible, how about this?
entity HIER is
port (
IN1 : in bit;
OUT1, OUT2 : out bit);
end hier;
architecture HIER_IMPL of HIER is
component BUF is
port (a : in bit; o : out bit);
end component;
begin
BUF1 : BUF port map (a => IN1, o => OUT1);
BUF2 : BUF port map (a => IN1, o => OUT2);
end HIER_IMPL;
Related
My codes for Alu and Mux:
module alu(input logic [31:0]srca, srcb,
input logic [2:0] alucontrol,
output logic zero,
output logic [31:0]aluout);
logic [31:0] addr, subr, sltr, Andr, Orr;
assign addr = srca + srcb;
assign subr = srca - srcb;
assign sltr = (srca < srcb) ? 1 : 0;
assign Andr = srca & srcb;
assign Orr = srca | srcb;
always_comb
begin
case(alucontrol)
3'b010: aluout = addr;
3'b110: aluout = subr;
3'b111: aluout = sltr;
3'b000: aluout = Andr;
3'b001: aluout = Orr;
default: aluout = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
endcase
zero = (subr == 0) ? 1 : 0;
end
endmodule
module mux2#(parameter WIDTH = 8)
(input logic [WIDTH-1:0] d0, d1,
input logic s,
output logic [WIDTH-1:0] y);
always_comb
begin
y = s?d1 : d0;
end
endmodule
and their instantiation under the same top module:
alu alu(srca, srcb, alucontrol, aluout, zero);
mux2 #(32) resmux(aluout, readdata, memtoreg, result);
When I try to connect my 2-1Mux resmux with my alu, the aluout doesn't get connected to resmux
aluout gets suspended
I could solve this by exchanging the order of aluout and zero, but could anybody explain why this happens and how to avoid? Thanks a lot!
There are a number of mechanisms for connecting ports in SystemVerilog. The mechanism you are using is positional. That means each signal connection has to go in the prescribed order that they appear in the module declaration of alu. The way your code is written, the signal zero in module top is connected to last port aluout declared in module alu.
SystemVerilog also has a by_name syntax .portname(signal). You can list all your port connections in any order that way.
alu alu(.srca(srca), .srcb(srcb), .alucontrol(alucontrol), .alu(aluout), .zero(zero));
When the signal name you are connecting matches the declared port name, you can just use .portname.
alu alu(.alucontrol, .aluout, .zero, .srca, .srcb);
And finally, if all the port names match the signal names, you can use a wildcard, .* as well as list exceptions explicitly
alu alu(.*, .zero(my_zero));
I have this 4 bit ring counter that I'm trying to make, and I feel like I'm so close, but I can't figure out how to make one input depend on the previous state's output. Here's what I have:
`default_nettype none
// Empty top module
module top (
// I/O ports
input logic hz100, reset,
input logic [20:0] pb,
output logic [7:0] left, right
);
// Your code goes here...
q[3:0];
assign q[3:0] = right[3:0];
hc74_set setFF(.c(pb[0]), .d(pb[1]), .q(right[0]), .sn(pb[16]));
hc74_reset resetFF1(.c(pb[0]), .d(pb[1]), .q0(right[1]), .rn(pb[16]));
hc74_reset resetFF2(.c(pb[0]), .d(pb[1]), .q1(right[2]), .rn(pb[16]));
hc74_reset resetFF3(.c(pb[0]), .d(pb[1]), .q2(right[3]), .rn(pb[16]));
endmodule
// Add more modules down here...
// This is a single D flip-flop with an active-low asynchronous set (preset).
// It has no asynchronous reset because the simulator does not allow it.
// Other than the lack of a reset, it is half of a 74HC74 chip.
module hc74_set(input logic d, c, sn,
output logic q, qn);
assign qn = ~q;
always_ff #(posedge c, negedge sn)
if (sn == 1'b0)
q <= 1'b1;
else
q <= d;
endmodule
// This is a single D flip-flop with an active-low asynchronous reset (clear).
// It has no asynchronous set because the simulator does not allow it.
// Other than the lack of a set, it is half of a 74HC74 chip.
module hc74_reset(input logic d, c, rn,
output logic q, qn);
assign qn = ~q;
always_ff #(posedge c, negedge rn)
if (rn == 1'b0)
q <= 1'b0;
else
q <= d;
endmodule
This is on an FPGA simulator, which is why there are a few things like pb (these are push buttons) and left, right outputs which are sets of 8 LEDs each.
Let's first make sure we are on the same page
Based on wikipedia description of a ring counter
This could be implemented as follows:
module top (
// I/O ports
input logic reset_n,
input logic clk,
output logic [3:0] ring
);
// Your code goes here...
always #(posedge clk or negedge reset_n) begin
if(~reset_n) begin
ring = 4'b0001;
end
else begin
ring[0] <= ring[3];
ring[1] <= ring[0];
ring[2] <= ring[1];
ring[3] <= ring[2];
end
end
endmodule
The output ring is a 4-bit one hot vector, reset_n = 0 makes ring = 0001 every clock with reset_n = 1 rolls the ring to the right, [0001, 0010, 0100, 1000, 0001, ...].
But you want to use instances of the flops you defined. Notice that in an assignment a <= b, a is the output of the flop (q port), and b is the input of the flop (d port).
module top (
// I/O ports
input logic reset_n,
input logic clk,
output logic [3:0] ring
);
// Your code goes here...
hc74_set setFF(.c(clk), .d(ring[3]), .q(ring[0]), .sn(reset_n));
hc74_reset resetFF1(.c(clk), .d(ring[0]), .q0(ring[1]), .rn(reset_n));
hc74_reset resetFF2(.c(clk), .d(ring[1]), .q1(ring[2]), .rn(reset_n));
hc74_reset resetFF3(.c(clk), .d(ring[2]), .q2(ring[3]), .rn(reset_n));
endmodule
You have to connect the ports accordingly, I just used clk for the clock and reset_n for the negated reset signal.
I 'm trying to use emacs flycheck for vhdl coding environment.
My problem is that flycheck cannot recognize packages and records in the packages and show warning such that "unit xx not found in library work"
I have also set (custom-set-variables '(flycheck-ghdl-workdir "/XXX/tWork/RTL/Mult/src/vhdl")) to show the directory of the source code to the flycheck
warning in emacs vhdl
How can i configure flycheck appropriately.
PS: below is new edit:
Let me clear this things first.
I have vhd file that includes a package as follows:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.multPckg.all;
entity mutl is
port(
iClk : in std_logic;
iRst : in std_logic;
iData : in dataInRecord;
);
end entity mutl;
architecture RTL of mutl is
signal dataIni1 : dataInRecord := cDataInRecord;
signal dataIni2 : dataInRecord := cDataInRecord;
--signal x : std_logic;
begin
--x <= osman;
inRegPro : process (iClk) is
begin
if rising_edge(iClk) then
dataIni1 <= iData;
dataIni2 <= dataIni1;
end if;
end process inRegPro;
end architecture RTL;`
and the multPckg is in the same directory and coded by me
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package multPckg is
constant dataInBitW : integer := 8;
constant dataOutBitW : integer := 8;
type dataInRecord is record
in1 : std_logic_vector(dataInBitW-1 downto 0);
in2 : std_logic_vector(dataInBitW-1 downto 0);
end record dataInRecord;
constant cDataInRecord : dataInRecord := ((others => '0'), (others => '0'));
end package multPckg;
package body multPckg is
end package body multPckg;
emacs warn me about the line use work.multPckg.all; because of it cannot find the library work. Is there any way for emacs flycheck to find the work.multPckg not to give that warnings.
I hope i'm clear about the issue.
Hey I'm working in project, but i cant manage to connect from a IP not located in the same network (LAN). The code bellow works fine locally, but I cant figure out how to make work from different IP located in different locations?, and google cant see to help, any ideas?
class
RG_NETWORK_SERVER
inherit
STORABLE
NETWORK_SERVER
redefine
receive,
received,
close
end
create
make_server
feature
connections: LINKED_LIST [RG_CONNECTION]
max_to_poll: INTEGER
message_out: RG_MESSAGE
received: detachable RG_MESSAGE
poll: MEDIUM_POLLER
make_server
require
local
l_message_out: detachable like message_out
l_connections: detachable like connections
l_in: detachable like in
do
make (1337)
max_to_poll := 1
create poll.make_read_only
in.set_non_blocking
l_in := in
create l_message_out.make
message_out := l_message_out
create l_connections.make
connections := l_connections
connections.compare_objects
execute
end
process_message
local
stop: BOOLEAN
pos: INTEGER
do
from
connections.start
until
connections.after or stop
loop
if connections.item.is_waiting then
if attached {RG_MESSAGE} retrieved (connections.item.active_medium) as l_message_in then
if l_message_in.new then
connections.item.set_client_name (l_message_in.client_name)
create message_out.make
message_out.set_client_name (l_message_in.client_name)
message_out.extend (l_message_in.client_name)
message_out.extend (" has just joined the server%N")
elseif l_message_in.over then
poll.remove_associated_read_command (connections.item.active_medium)
connections.remove
create message_out.make
message_out.set_client_name (l_message_in.client_name)
message_out.extend (l_message_in.client_name)
message_out.extend (" has just gone%N")
stop := True
else
message_out := l_message_in.deep_twin
message_out.put_front (" has just sent that :%N")
message_out.put_front (message_out.client_name)
message_out.put_front ("-> ")
end
pos := connections.index
-- l_message_in.print_message
message_out.print_message
broadcast
connections.go_i_th (pos)
-- Post status to client
create message_out.make
message_out.extend ("Got it! %N")
message_out.independent_store (connections.item.active_medium)
end
end
if not stop then
connections.forth
end
end
end
broadcast
local
client_name: detachable STRING
do
client_name := message_out.client_name
if client_name /= Void then
from
connections.start
until
connections.after
loop
if connections.item.client_name /~ client_name then
message_out.independent_store (connections.item.active_medium)
end
connections.forth
end
end
end
receive
do
in.accept
if attached {like outflow} in.accepted as l_outflow then
l_outflow.set_blocking
new_client (l_outflow)
end
from
connections.start
until
connections.after
loop
connections.item.initialize
connections.forth
end
poll.execute (max_to_poll, 1000)
end
new_client (a_flow: attached like outflow)
local
new_connection: RG_CONNECTION
do
if max_to_poll <= a_flow.descriptor then
max_to_poll := a_flow.descriptor + 1
end
create new_connection.make (a_flow)
connections.extend (new_connection)
create message_out.make
message_out.extend ("Welcome! %N")
message_out.independent_store (a_flow)
poll.put_read_command (new_connection)
end
end
and the client:
class
RG_NETWORK_CLIENT
inherit
NETWORK_CLIENT
redefine
received
end
create
make_join
feature
make_join(ip:STRING)
require
is_ip_void : ip /= Void
local
l_client_name: detachable like client_name
do
check_name
l_client_name := client_name
make (1337, ip)
max_to_poll := in_out.descriptor + 1
create connection.make (in_out)
create poll.make_read_only
poll.put_read_command (connection)
send_name_to_server
auto_scan_server
processing
end
feature
connection: RG_CONNECTION
std_input: detachable RG_CONNECTION
message_out: RG_MESSAGE
received: detachable RG_MESSAGE
client_name: STRING
over: BOOLEAN
poll: MEDIUM_POLLER
input_poll: detachable MEDIUM_POLLER
max_to_poll: INTEGER
waiting:BOOLEAN
send_name_to_server
do
create message_out.make
message_out.set_client_name (client_name)
message_out.set_new (True)
message_out.set_over (False)
send (message_out)
end
processing
do
from
over := False
until
over
loop
scan_from_server
if not over then
read_content
end
end
cleanup
end
read_content
local
temp: detachable STRING
do
io.put_string ("Enter message: ")
io.readline
temp := io.laststring
if temp /= Void and not temp.is_empty then
if temp.is_equal ("bye") then
over := True
end
create message_out.make
message_out.extend (temp)
message_out.extend ("%N")
message_out.set_over (over)
message_out.set_client_name (client_name)
message_out.set_new (False)
send (message_out)
auto_scan_server
end
end
check_name
local
l_name: detachable STRING
do
io.putstring ("Enter your name : ")
io.readline
l_name := io.laststring
check
l_name_attached: l_name /= Void
end
client_name := l_name.twin
end
scan_from_server
local
l_received: like received
do
connection.initialize
poll.execute (max_to_poll, 1000)
if connection.is_waiting then
receive
l_received := received
if l_received /= Void then
waiting := FALSE
l_received.print_message
if l_received.over then
over := True
end
end
end
end
auto_scan_server
do
waiting := True
from until not waiting
loop
scan_from_server
end
end
end
The work around is the work with the samples provided from Eiffel, it works as longest the two persons are connected in the same network. for example as follow:
Here we define if the user has receive the message or is waiting for one, also redefine the poll_command to be able to use it.
inherit
POLL_COMMAND
redefine
make
end
create
make
feature {NONE} -- Initialization
make (s: IO_MEDIUM)
do
Precursor (s)
create client_name.make_empty
end
feature
is_waiting: BOOLEAN
client_name: STRING
execute (arg: ANY)
do
is_waiting := True
end
initialize
do
is_waiting := False
end
set_client_name (s: STRING)
require
s_exists: s /= Void
do
client_name := s.twin
end
end
Then following the chat sample, that can be found in the samples folder, in the message handler, we create the follow:
set_client_name (s: STRING)
require
s_not_void: s /= Void
do
client_name := s.twin
end
set_new (flag: BOOLEAN)
do
new := flag
end
Later in the connection class we are able to connect to a server ip, which it can be pass true command line or via GUI input.
make_join (name: STRING; ip: STRING; gc: RG_CLIENT)
require
is_ip_void: ip /= Void
do
-- Connects to IP on port 1337
make (1337, ip)
max_to_poll := in_out.descriptor + 1
create connection.make (in_out)
create poll.make_read_only
poll.put_read_command (connection)
-- Sets client name and refrence
client_name := name
p_client := gc
-- Sends name to server and receives ID
client_id := send_name_to_server
-- Launches instance as thread
make_thread
launch
execute
end
Then in the server class...
make_server (gs: RG_SERVER)
local
l_message_out: detachable like message_out
l_connections: detachable like connections
l_in: detachable like in
do
-- Instantiate reference and create server listening on port 1337
game_server := gs
make (1337)
max_to_poll := 1
create poll.make_read_only
in.set_non_blocking
l_in := in
create l_connections.make
connections := l_connections
connections.compare_objects
-- Launches instance as tread
make_thread
launch
end
There is a bit more code, but this is a good sample in how to do it, there must be a method to handle the connections, but this is a good start, also remember that all this is based on their samples, chat sample is a good point of start..
enjoy eiffel while is not crashing .
I have modeled 4 bit Ring Counter using D Flip Flop.
The D flip flop is in separate file, included in my workspace. The D flip flop works correctly (gives correct output waveform).
This is the code of ring counter:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ring4counter is
port (
clk: std_logic;
output: out std_logic_vector(3 downto 0));
end ring4counter;
architecture ring4counter_arch of ring4counter is
component dff
port (
clk: std_logic;
d: in std_logic;
q: out std_logic;
qbar: out std_logic);
end component;
signal temp:std_logic_vector(3 downto 0):=(others=>'0');
begin
r1: dff port map(clk, temp(3), temp(0));
r2: dff port map(clk, temp(0), temp(1));
r3: dff port map(clk, temp(1), temp(2));
r4: dff port map(clk, temp(2), temp(3));
output <= temp;
end ring4counter_arch;
Here is the testbench code for Ring counter:
library ieee;
use ieee.std_logic_1164.all;
entity ring4_tb is end ring4_tb ;
architecture arch of ring4_tb is
component tbc is
port (
clk: std_logic;
output: out std_logic_vector(3 downto 0));
end component ;
component dff
port (
clk: std_logic;
d: in std_logic;
q: out std_logic;
qbar: out std_logic);
end component;
constant period : time := 50 ns ;
signal clk : std_logic := '0' ;
signal done : boolean := false ;
signal output : std_logic_vector(3 downto 0) ;
shared variable cycle : natural := 0 ;
signal temp:std_logic_vector(3 downto 0):=(others=>'0');
begin
-- this is the unit under test
u1: tbc
port map(
clk => clk,
output => output) ;
clkprocess: process(done, clk)
begin
if (not done) then
if (clk = '1') then
cycle := cycle + 1 ;
end if ;
clk <= not clk after period / 2 ;
end if ;
end process ;
r1: dff port map(clk, temp(3), temp(0));
r2: dff port map(clk, temp(0), temp(1));
r3: dff port map(clk, temp(1), temp(2));
r4: dff port map(clk, temp(2), temp(3));
output <= temp;
testbench: process
begin
wait until (clk = '0') ;
temp <= "1000";
wait for period*4 ;
done <= true ; -- force the clock process to shutdown
wait ; -- this waits forever
end process ;
end arch ;
But the waveform for 'output' is 'U' for all bits.
Where am I going wrong?
In the testbench process when you are trying to initialize temp to "1000", the flip flops are still driving the temp signal as well, so you effectively have a bus fight going on.
Use the initialisation of temp in your ring counter to set up the signal.
Note that this may not synthesize correctly depending on your architecture and synthesis tool.
The most general purpose way of doing it is to add a reset signal to all the DFFs except on, and put a preset signal on that one. Then you assert the reset at the start, which will set up the DFFs to a good value.
Here's a simpler version of your code which does that and avoid the need to use explicit DFFs. You can also change the width of temp and the code will do all the rest for you:
process (clk)
begin
if reset = '1' then
temp <= (0=>'1', others => '0'); -- set one bit high, the others low.
elsif rising_edge(clk) then
-- take the high bit and move it to the low bit.
-- Move the other bits left 1 place
temp <= temp(temp'high-1 downto 0) & temp(temp'high);
end if;
end process;
(Note: code just typed into the message, there may be syntactic typos in there!)
BTW, shared variables are a bad idea unless they are of protected types. They can have race conditions.
One thing to do is add a enable signal to D flipflops. when you want to reset the circuit make the enable signal go low and then change the temp to "1000".
r1: dff port map(clk, temp(3), temp(0), enable);
process(clk,reset)
begin
if(rising_edge(clk)) then
if( reset='1') then
enable='0';
temp <= "1000";
else
enable <= '1';
end if;
end if;
end process;