Verilog 'for'-loop returned values - simulation

Question

I have written the code below.
My problem:
At index 1
It enters in the for loop with some values. It goes in a 'if' statement and as you can see there the last instruction from every 'if' it is something like 'P=....' .
At index 2 (next step )
It enters in a 'if' statement but the value of P is not from step 1, it is the initial value .
How can I use the last value of 'P' at next step ? (index+1 )
module multiplier(prod, a, b, wireP, wireA, wireS);
output [15:0] prod;
output [16:0] wireA;
output [16:0] wireS;
output [16:0] wireP;
reg [15:0] prod;
input [7:0] a;
input [7:0] b;
reg [16:0] P;
reg [16:0] S;
reg [16:0] A;
wire [16:0] tempshift;
reg [16:0] tempoutshift;
arithmeticShift shiftP(tempshift,P);
wire [16:0] tempPS;
reg [16:0] tempoutPS;
carryForPbooth sumPS(coutPS,tempPS,P,S,0);
wire [16:0]tempPA;
reg [16:0]tempoutPA;
carryForPbooth sumPA(coutPA,tempPA,P,A,0);
reg [16:0] regP;
reg [16:0] regA;
reg [16:0] regS;
integer index;
always #(*) begin
A[16:9] = a[7:0];
A[8:0] = 9'b000000000;
S[16:9] = ~a[7:0]+1'b1;
S[8:0] = 9'b000000000;
P[16:9] = 8'b00000000;
P[8:1] = b[7:0];
P[0] = 1'b0;
#1 tempoutPS = tempPS;
#1 tempoutPA = tempPA;
#1 tempoutshift = tempshift;
for(index = 1; index < 9; index = index + 1) begin
if((P[1:0] == 2'b00) | (P[1:0] == 2'b11)) begin
#1 tempoutshift = tempshift;
#1 P = tempoutshift;
end
if(P[1:0] == 2'b01) begin
#1 tempoutPA = tempPA;
#1 P = tempoutPA;
#1 tempoutshift = tempshift;
#1 P = tempoutshift;
end
if(P[1:0] == 2'b10) begin
#1 tempoutPS = tempPS;
#1 P = tempoutPS;
#1 tempoutshift = tempshift;
#1 P = tempoutshift;
end
end
#1 prod=P[16:1];
end
assign wireP = P;
assign wireS = S;
assign wireA = A;
endmodule

Answer 1

It looks like you are trying to create a synthesizable Shift and Add multiplier architecture where the multiply value is calculated over 9 clock cycles.
Looking through the code and removing some temp variables I have reduced it down to:
module multiplier(
input [7:0] a,
input [7:0] b,
output [15:0] prod,
output reg [16:0] A,
output reg [16:0] S,
output reg [16:0] P
);
wire [16:0] tempshift;
arithmeticShift shiftP(tempshift,P);
wire [16:0] tempPS;
carryForPbooth sumPS(coutPS,tempPS,P,S,0);
wire [16:0] tempPA;
carryForPbooth sumPA(coutPA,tempPA,P,A,0);
reg [3:0] index;
always #(*) begin
A = { a, 9'b000000000};
S = { -a, 9'b000000000} ;// -x => ~x+1
P = {8'b00000000, b, 1'b0};
for(index = 1; index < 9; index = index + 1) begin
if((P[1:0] == 2'b00) | (P[1:0] == 2'b11)) begin
#1 P = tempshift;
end
if(P[1:0] == 2'b01) begin
#1 P = tempPA;
#1 P = tempshift;
end
if(P[1:0] == 2'b10) begin
#1 P = tempPS;
#1 P = tempshift;
end
end
end
assign prod = P[16:1];
endmodule
I think you are faking clock cycles using #1, This will only work in the simulator will either not synthesise or only the last assignment will take effect.
If this is meant to be split over 9 clock cycles the it need to have a counter tied to the shift value, not a for loop. In Verilog for loops are unrolled at compilation time and should be executable in zero time, unless used as part of a testbench.
The sections of code similar to the following appear several times.
#1 P = tempPA;
#1 P = tempshift;
I think you are trying to apply a value to a module then capture its output, using the same variable, this is hard to know as I do not have the interfaces for the blocks you have instantiated. You can not do this in Verilog if you want to synthesize your code. You should be using another intermediate variable to connect things up.
Remember that always #* begin ... end is combinatorial logic, and has no timing except the ripple involved in calculating the answer. For implying a D-Type flip-flop we use:
always #(posedge clk or negedge rst_n) begin
if (~rst_n) begin
// Reset conditions
end
else begin
// Next clock conditions
end
end