I want to make XOR gate using OR gate.I have tried but I have to use additional NOT gate to make an XOR gate. Is it possible to make an XOR gate using only OR gate? If so how can I do this? please help. thanks in advance.
The AND and OR functions are "monotone". By definition, this means if you start with any setting of input bits, then change one of the input bits from zero to one, the output can either stay the same or change from zero to one; it can never change from one to zero. You can prove this from the truth tables.
A composition of monotone functions is a monotone function. This is also easy to prove.
XOR is not a monotone function. (Consider a two-input XOR where both inputs are one, then change one to zero.)
Therefore, it is impossible to do what you are asking.
There is no SoP or PoS equation that will allow you to perform XOR with only OR gates; a minimum of 3 (non-XOR/XNOR) gates is required, including at least one inversion.
Although you cannot make a XOR Gate only with OR Gates, something you can do is have the same inputs (A and B) that you had running through the OR Gate connect to a NAND Gate. The outputs of the OR Gate and the NAND Gate would then be connected through an AND Gate. There is a simpler way to create a XOR Gate using this method.
Related
I'm reading the Digital Design and Computer Architecture by David Harris, Sarah Harris. The authors give the following definition of combinational logic:
A combinational circuit’s outputs depend only on the current values of
the inputs; in other words, it combines the current input values to
compute the output... A combinational circuit is memoryless, but a
sequential circuit has memory. The functional specification of a
combinational circuit expresses the output values in terms of the
current input values.
However, they claim this circuit is not combinational:
because "node n6 connects to the output terminals of both I3 and I4". Indeed, it's one of the designated signs when a scheme can not be combinational but, according to the authors:
Certain circuits that disobey these rules are still combinational, so
long as the outputs depend only on the current values of the inputs.
As I'm able to catch on, the aforementioned circuit is the case: its output is 1 if and only if its inputs are both 1, otherwise the output is 0. So the output is defined as a function of the inputs (the AND function).
In fact, there was already a question about this circuit in the computer science network and it has an accepted answer. Here's an excerpt from it:
Circuit (d) cannot be written in this form [of formula], since the
outputs of I3 and I4 are wired together. What is the relation between
the input to the rightmost gate and the outputs of I3 and I4? Not
something that can be described combinatorially.
Unfortunately, I'm still confused due to
The circuit, regarded as a black box, is still in scope of the combinational logic definition: its output values depend only on the current values of the inputs;
The relation between the input to the rightmost gate and the outputs of I3 and I4 can be described through the function NAND of the circuit inputs and this function is quite "memoryless". It's not obvious for me why we can't afford to depict a gate input using multiple outputs of other gates.
I need some elaboration. Maybe things would fall into place if someone provide a circuit example when two gates outputs is connected to one input and it actually causes "memory" (in contrast to the considered sample).
Circuit (d) is not combinational because it is not a logic gate circuit at all.
I think it's a very silly example to explain combinational vs sequential circuits.
In a logic circuit, an output wire cannot go to another output wire. You assumed that the outputs, when connected together, will act as a logical OR or AND of themselves.
This is not true (otherwise why would we use AND/OR gates in the first place?).
What will happen depends on the specific implementation of the gates (i.e. specific IC or manufacturing process you used) and this is not something that a logic circuit is meant to model.
A logic circuit must behave the same, no matter what brand you are using.
In circuit (d), the output of I3 will feed both the input of the rightmost NOT and the output of I4 (the complementary is also true).
Most IC will break if a current will flow in from their outputs, others won't but they will interfere with the capability of the right-most NOT to sense its input.
Logic circuits are still circuits, so you should, in theory, perform a full circuit analysis, which includes solving differential equations, to solve for their output.
Digital electronics is a branch that abstracts from these "low-level" details but at the cost of making some assumptions, one of which is: outputs are never merged without a gate.
The whole point of a combinational circuit is that you can write out = f(in0, in1, ..., ink) but it's not always possible.
Take for example an edge detector, it is just a f(A) = (NOT A) AND A which should, by the law of the excluded middle, always output 0.
But it will not because the NOT A path takes a slightly longer time to reach the AND input.
How can you describe this dynamic behaviour with a f(A) function?
Don't think too much of it, when you'll get to sequential circuits you'll spot the difference immediately (if you need a preview, look up for "latch circuit").
It is very confusing while googling for LSTM gates , I find that some references and articles say that they are three gates: input , forget and output gates , While others say that they are four gates : learn , forget , remember, and use gate ?
So, what is the right ?
There are four gates: input modulation gate, input gate, forget gate and output gate, representing four sets of parameters.
We can see that there are four sets of parameters(8 matrices) colored in blue in the below graph of LSTM where f stands for the forget gate, g and i the add gate, o the output gate. Since the add gate needs two sets of parameters we can combine them as just one gate.
Reference:
Speech and Language Processing
Long Short Term Memory networks – usually just called “LSTMs” – are a special kind of RNN, capable of learning long-term dependencies. So there are different types of LSTMs, LSTMs have chain-like structure like RNN, but the repeating module has a different structure. Instead of having a single neural network layer, there are four, interacting in a very special way. However, there are many variants of LSTMS.
Ref: http://colah.github.io/posts/2015-08-Understanding-LSTMs/
I have created my truth table and drawn from this a boolean expression (f = B'A' + CA' + DC' + DB + D'CB') which I have then attempted to convert into a circuit using Quartus.
I am new to digital logic and I need some help from someone wit experience who can tell me if what I have attempted looks correct.
I am unable to compile the circuit as I don't have 'device support installed'. If anyone could point me in the right direction for how to obtain that, that would be greatly appreciated.
This is the circuit I created based on the boolean expression.
This is my truth table. The circuit corresponds to the f column
Everything to the left of your AND gates looks mathematically correct (although not very efficient). You can drastically reduce the amount of NOT gates used.
Instead of splitting the signals before the NOT gates and having each individual branch have its own NOT gate, you can split the signals after the NOT gate thus reducing the total amount of NOT gates used.
Anyway, the fundamental reason your circuit is invalid is because of the very right part of it, here:
You are shorting together the outputs of two gates, which is not allowed. A single node cannot simultaneously have two separate voltages.
What you need to do to fix this problem is take each individual output of your 5 AND gates and take them all to a separate input of a 5-input OR gate.
Something like this:
If this software package that you are using doesn't support five inputs to a gate, then you can split it up like so:
I'm playing with a neural network I implemented myself: it's a trivial forward network using RPROP as a learning algorithm as the only "plus" compared to the basic design.
The network scores decently when I test it against MNIST or when I attempt at image compression, but when I try to model something as simple as the XOR function, sometimes during learning it gets trapped into a local minima, and outputs the following truth table:
0 XOR 0 = 1.4598413968251171e-171
1 XOR 0 = 0.9999999999999998
0 XOR 1 = 0.9999999999999998
1 XOR 1 = 0.5
Often the result after the training is correct, but sometimes 1 XOR 1 outputs 0.5 instead of 1 as it should. It does not really always happens with XOR(1,1), but with other inputs as well. Being the XOR function a "classical" in the literature of back propagation I wonder what's happening here, especially given that my network appears to learn more complex (but perhaps less non-linear) tasks just fine.
My wild guess is that's something wrong with the biases.
Any hint?
Note 1: the network layout above is 2|3|1, but does not change much when I use more hidden units, certain learning attempts still go wrong.
Note 2: I put the implementation into a Gist: https://gist.github.com/antirez/e45939b918868b91ec6fea1d1938db0d
The problem was due to a bug in my implementation: the bias unit of the NN immediately before the output unit was not computed correctly. After fixing the code the XOR function is always computed right.
If I'm getting a anonymous operator from a user I would like to test (extremely quickly) if the operator is linear. Is there a standard way to do this? I have no way of doing symbolic operators, or parsing the function. Is the only way trying some random functions (what random functions do I choose) and seeing if they satisfy linearity??
Thanks in advance.
Context:
User supplies a black box operator, that is a function which takes functions to functions.
I can give the operator a function and I get a function back. I want to determine if the operator is linear? Is there a standard fast method which gives me high confidence?
No, not without sweeping the entire parameter space. Imagine the following:
#(f) #(x) f(x) + (x == 1e6)
This operator is non-linear, but there's no way of knowing that unless you happen to test at x == 1e6.
UPDATE
As others have suggested, it may be "good enough" to determine a domain of interest, and check for linearity at periodic intervals across the domain. This may give you false positives (i.e. suggest an operator is linear when in fact it's non-linear), but never false negatives.
This is information the user should supply. Add a parameter linear true/false, default to false (I'm assuming that the code for non-linear will work for linear too, just taking more time).
The problem with random testing is that you will classify a non-linear function as linear sooner or later, and then the user has a problem, because your function unpredictably produces wrong results (depending on which points you pick randomly), that may be reasonably close to the correct results, ie people may not notice for a loooong time --> this is a recipe for disaster.
Really, the user should know this in the first place, its very important to avoid false positives and as said before there is no completely reliable way to test this. Save yourself the trouble and add an additional parameter.