My Problem
I want to model a block called "confirmer". The specification is that the output will SIMPLY be the delayed version of input based on an edge (rising/falling). To clarify, I will try to put the timing diagrams below:
___________________________
| |
Input _______| |____________________________
(Tdelay) _____________________
| |
Output ______________| |____________________________
And
____________________________
| |
Input _______________| |____________________________
(Tdelay)
______________________________________
| |
Output _______________| |_____________________
As I tried to draw above, the rising edge means that my output will simply follow the change input after Tdelay. But when it changes back from 1 to 0, there is no delay. This is the diagram for a confirmer block that is rising edge triggered.
For a falling-edge triggered confirmer, it is the opposite. When there is a falling edge, the output will follow the change in input after Tdelay seconds i.e. hold the last input for Tdelay.
My Target Platform
SIMULINK and MATLAB.
My initial solution
I know that there is way to trigger for certain actions by using a triggered subsystem block. But I am struggling to use the delay/unit-delay block in SIMULINK to implement the delay with the trigger. I have managed to use another block called resettable delayer but it does not work properly when it is a rising-edge reset; it simply resets based on an edge.
Has anyone tried this kind of problem before?
Update since #PhilGoddard's answer
I think this should work as I have managed to reproduce the timing diagrams in the question.
How I designed it:
1) Used the repeating sequence stair as my input.
2) configured the unit delay block such that the reset is enabled at rising edge or fallling edge. This will allow either of the following"
i) Input (falling edge) = Output (falling edge) [rising edge is delayed by Tdelay
ii) input (rising edge) = Output (rising edge) [failling edge is delayed by Tdelay]
Unless I am losing my marbles, I think that this solution is okay?
Use an Enabled and Triggered Subsystem.
Drag that block from the Ports and Subsystems library, and make only two changes to its properties: Open the subsystem, open the outport (called Out1), and change the "Output when disabled" property to "reset" and the "Initial Output" to 0.
Then, feed your input into the enable port; feed a delayed version of your input into the trigger port (which by default is set to be rising edge); and feed a constant block (with value=1) into the signal inport.
The output of the subsystem should be as desired.
This is my solution for case 2 of the proposed problem. The output is the sum of two signals of opposite value which is increased at every rising or falling edge of the trigger signal. It is very likely an overkill and there is probably a much easier solution but the proposed solution did not work for me and this did.
My solution:
How the counter is created (credit to How to create a counter in simulink):
Try On/Off delay. It perfectly meets your demand.
(There should be its icon but It seems that I cannot post image with under 10 reputation)
The description from the help page says:
The On/Off Delay block implements the following logic when the Select type parameter is set to On delay:
When the input becomes true, the output becomes true after a preset time delay. The output remains true as long as the input is true.
When the input is false or becomes false, the output becomes false with no delay.
When the Initial condition of previous input parameter is set to 1, and the input is true at t = 0, the output is true with no delay.
The On/Off Delay block implements the following logic when the Select type parameter is set to Off delay:
When the input becomes false, the output becomes false after a preset time delay. The output remains false as long as the input is false.
When the input is true or becomes true, the output is true with no delay.
When the Initial condition of previous input parameter is set to 0, and the input is false at t = 0, the output is false with no delay.
falling edge delay
rising edge delay
Related
I need to write a uni directional analog switch in Systemverilog with some delay and rise and fall times.
input real in;
output real out;
assign #<delay> out = (enable === 1'b1)?in:0.0;
With above, I do not see any delay and output is exactly same as input with enable = 1. Is there a way I can add delays and rise/fall times to the above?
rise/fall delays are not defined for anything other than integral values.
I have an audio file that I read with [tabread~]). The audio starts with some silence and I am trying to find the first non silent sample index.
I have tried to use [bonk~], [fiddle~] or [sigmund~] but the results were approximate and not constants.
Does anyone have a solution for this? Thanks.
Pascal
I already answered this question in the Pure Data forum, but I am copying it here (slightly adapted) in case someone else find it useful:
If the sound completely silent up to the point you marked (that is, is the table filled with zeroes up to that point) then you can simply go through the array's elements using [tabread ], starting at the first sample and checking if the absolute value of the subsequent ones is larger than zero. If the signal is not completely silent but near silent, then you will can either use sort of attack detection (such as [bonk~]) or simply use something like this:
...
|
[tabread array1]
|
{abs]
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[> 0.001]
|
[sel 1]
|
...
Note how I used [> 0.001] instead of [> 0]. Adjust this number (either directly as an argument or via the rightmost inlet of [>]) to control the sensitivity of the detection. Then once [sel 1] receives a float of value 1, you can use its bang to stop the process since you found your first non-silent element.
I am building a block for this equation Y_New= Lambda*(X_t) + (1-lambda)*Y_old,
I would like to have Y_old as the delayed value by one step to Y_New .. and this to happen continuously.ยด. and not only one time.. so i have the value of Y_old updated every time Y_New changes ... If just a unit delay block.. it does not give me the right answer.. what i am thinking of is the unit delay reset.. but i do not know what is the Input of the reset port.. I connected it to am if Action Subsystem but it gives me an error that i can only connect the if Action Subsystem to one port.. i want to link the unit delay reset to an if condition that results if it is true then update Y_old.. if not Y_New = Y_oldenter image description here
From what you describe, I do not think you need the reset port. You should turn off the reset port and place the Delay block inside an enabled sub-system. Whenever the enable signal is on delay will update with a new value otherwise, it will hold on to the existing value. I assume you have some signal which tells when y signal has new value.
If your y signal is updated each time step then you should not use enabled subsystem. It is simpler to just use the delay without reset port. At each time step when you get a new value, delay will update with the new value and will output the old value.
Question
Is there a way to enforce the simulation step to be smaller than a compile-time constant in a simulink model?
Context
I'm trying to build a PWM block on simulink. As it is now, I have to make sure that the user chooses a step size responsibly (smaller than half the period chosen by him), otherwise the block behaves abnormally. The only way I came up was to stop the simulation if the step size is not small enough, but I find that very annoying (as a user). If possible, I'd like for the user to not worry about this at all.
Here's what I would do: add the following pseudo-code to the block callback StartFcn:
T_PWM = get_param(gcb,...); % get the block parameter (period) of the current PWM block (string)
T_PWM = str2double(T_PWM);
T_solver = get_param(bdroot,'FixedStep'); % get fixed used by the solver (string)
T_solver = str2double(T_solver); % convert from string to double
if T_solver > 0.5*T_PWM
error('Solver step size must be smaller than half the PWM period')
end
I am trying to implement a counter logic in SIMULINK where
in1, in2 are inputs
out1 is the output
if in2 = 0, out1 = 0;
if in2 = 1, out1 = 1 after x high edges of in1
I have tried using "Detect Rise Positive" block but failed miserably because I don't have sufficient experience of implementing a timing diagram correctly in SIMULINK. Could anyone kindly point me to the right direction?
Update
An approach I have taken since I posted this question is the "Triggered and enabled subsystem". I am trying to set it up so that:
in2 becomes the enable signal
in1 becomes the trigger
in2 becomes the intput to the subsystem
Out1 becomes the output of the subsystem
But I think that the above was rubbish. Unfortunately it is not VHDL where I could have implemented it using 4-5 lines of description of the hardware logic.
Using a Triggered and Enabled subsystem is the right approach, but your inputs (and no doubt what's inside the subsystem) needs to be modified.
Don't have any input to the subsystem (other than the trigger and enable signals).
Inside the subsystem,
set the enable block property to reset the state when disabled.
set the outport property to reset when disabled and give the initial condition as 0.
create a counter out of a constant (value=1), a summation and a unit delay block.
feed the counter into a Compare to Constant block set to the 'x' value in your question.
feed that block to the outport.
When enabled, the counter should count the required number of steps (when triggered) before the output goes high.
A counter logic can be implemented very easily in simulink. Take a switch,give the control input as int1. If int1 is 1 ur output shuld be 0 else take another switch give its control input as int2. if int2 is 1 ur output shuld be 1+ previous value given in feedback funit delay block