SystemVerilog better way to copy a class - system-verilog

Which of the two copy functions are better?
A. Using reference to a function parameter:
function void copy(ref MyClass copyme);
MyClass copyme = new this;
endfunction
B. Returning a newly instantiated copy:
function MyClass copy();
return new this;
endfunction

Something like A is preferred for copy(). Use clone() for create then copy. Copy and clone are usually written as
class Myclass;
int A;
function void copy(Myclass rhs)
this.A = rhs.A;
endfunction
virtual function Myclass clone();
clone = new();
clone.copy(this);
endfunction
endclass
Note that clone is virtual, copy is non-virtual. Also, you do not need to pass class handles as ref arguments - class variables are already references.

Related

Distinguishing between local data member and child-class data member in an inline constraint

I have a class with a rand data member i. This class (child) is a member of class parent, which also has a data member i. I would like to constrain the value of i in the child class to be the same as the value of i in the parent class. I want to do something like:
c.randomize with {i==this.i;};
but the this.i doesn't seem to refer to the i data member of the parent class. (Why?)
I can do this:
function void f;
int dummy = i;
c.randomize with {i==dummy;};
endfunction
or this:
function void f;
c.randomize with {i==m.blk.p.i;}; // yuck!
endfunction
but wonder if there is a better (built-in, non-hacky) way of distinguishing between the two is.
MCVE:
class child;
rand int i;
endclass
class parent;
child c = new;
int i=1;
function void f;
c.randomize with {i==this.i;};
endfunction
endclass
module m;
initial begin : blk
parent p = new;
p.f;
$display("%p", p);
end
endmodule
https://www.edaplayground.com/x/2_8P
You want {i==local::i}. See section 18.7.1 of the 1800-2017 LRM
The reason this.i does not do what you expect is the combination of these two rules:
all class methods, including the built-in randomize method, have a built-in this argument. So c.method(args) is really method(args, c) and this becomes a variable local to the method set to the value of c
Identifiers within the with clause try to bind into the scope being randomized first before searching locally at the point where calling randomize().
So i and this.i refer to the same class variable just as if you wrote
class A;
bit i;
function void method;
i = 1;
this.i = 2;
endfunction
endclass

Why should be used in twice "new" in systemverilog?

Would you let me know why do we have to have the "new" keyword in twice in systemverilog?
​
class MyClass;
int number;
function new();
number = 0;
endfunction
endclass
module test;
MyClass test1 = new();
endmodule
As you can see, there are used in twice "new" keyword.
Could you let me know why do we need to use in twice?
function new();
number = 0;
endfunction
provides implementation of the function new(). When we call:
MyClass test1 = new();
we are creating test1. In order to create it, we call function new(), whose implementation we defined above. When we call new() it will ensure that property number of test1 is initialized to 0 (because that is what is happening inside of new()).
I hope my explanation is clear.

Is it possible to call new in SystemVerilog outside an assign statement?

This is how I usely call new in SystemVerilog:
class A;
endclass
A a = new();
But sometimes, I don't need a local object, I just want to send it directly to a function taking an A. Is there a way to call the new function explicitly here:
function use_a(A obj);
endfunction
use_a(new()); // <--- How to write this call to specify which new to call?
use_a(A::new()); // <--- new not expected here :(
Unfortunately, SystemVerilog's syntax does not allow this. The special new method is not a static method, and a class handle has to exist in some variable because of the way class memory management is defined. You could get around this by wrapping new around a static method:
class A;
static function A create();
create = new();
endfunction
endclass
...
use_a(A::create());
BTW, the UVM has create methods in the BCL and you almost never need to call new() directly.

Store reference to array/queue in SystemVerilog

I'd like to store a reference to an array/queue inside a class. It's doesn't seem possible to do this, though.
I'd like to do something like this:
class some_class;
// class member that points to the 'q' supplied as a constructor arg
??? q_ref;
function new(ref int q[$]);
this.q_ref = q;
endfunction
endclass
If q_ref is merely defined as int q_ref[$], then the assignment operator will create a copy, which isn't what I want. I'd like changes in 'q' to be visible inside the class.
Is there some hidden section in the LRM that shows how this can be done?
I'm not looking for the obvious "you have to wrap the array/queue in a class answer", but for something that allows me to interact with code that uses native arrays/queues.
There are only three variable types in SystemVerilog that can store references: class, event, and virtual interfaces variables.
You have to wrap the array/queue as a member in a class object. Then, any method of that class can be used in an event expression. Any change to a member of the class object causes a re-evaluation of that method. See the last paragraph and example in section 9.4.2 Event control of the 1800-2012 LRM.
So, the only solution for you would be to wrap the queue in a class. The latter is always assigned by a reference, as in this example:
class QueueRef #(type T = int);
T queue[$];
function void push_back(T t);
queue.push_back(t);
endfunction // push_back
endclass // Queue
class some_class;
QueueRef q_ref;
function new(QueueRef q);
this.q_ref = q;
endfunction
endclass
program test;
QueueRef q = new;
some_class c = new (q);
initial begin
q.push_back(1);
q.push_back(2);
$display(c.q_ref.queue);
end
endprogram // test

system verilog : Overridden members system verilog classes

class my_a;
int member1 = 1;
endclass
class my_ea extends my_a;
int member1 = 2;
endclass
Now when I do
my_a A;
my_ea EA;
EA =new();
A=EA;
EA = new(); has given handle to object of type my_ea to class variable EA.
A=EA; passes the same handle (pointer value which points to object of my_ea) to A. So, A.member1 should refer to value 2.
But it refers to value 1. Why?
So far, System-Verilog does not allow overriding of class variables. Only virtual methods can be overridden.
There is nothing like virtual for class members, so parent class can never directly access them. When using class_object.member, the particular class is referred to. Henceforth, this is not possible.
You cannot redefine an existing member by extending a class. You should use virtual methods to access (get/set) them. For instance, I added "get_member1" function to your code, and it returns 2 when called from a base class handle as you wanted.
class my_a;
int member1 = 1;
virtual function int get_member1();
return member1;
endfunction
endclass
class my_ea extends my_a;
int member1 = 2;
virtual function int get_member1();
return member1;
endfunction
endclass
module tb;
initial begin
my_a A;
my_ea EA;
EA =new();
A=EA;
$display("%0d", A.get_member1());
end
endmodule
You can similarly define "set_member1(int value)" function and use it to change its value.
In your case A.member1 should return the original member of its own class. When you are overriding a class members, you are basically hiding the overridden members. Super/base class can never access overridden member in its subclass.
As far as I know, only method identified with virtual, randomize() function and class constraint can be overridden without hiding them from the base class - thus they allow base class to reference to them (polymorphism)
For more info, please find here IEEE 1800-2012 in section 8.14 Overridden members.