Is it possible to have absolute delays specified in Sequences for assertions as shown below:
sequence Sab
a # 2ns b;
endsequence
This doesn't compile for sure. But I just wanted to know how to go about such situations when we want to write assertions for delays not in terms of clock cycles?
Eg: I want to write an assertion to check the skew relationship between 2 clocks? How do I specify an assertion to fire when the skew exceeds say 5 ps?
You use timing checks like $skew. See Section 31 of the IEEE Std 1800-2012 LRM
Related
I have been reading https://en.wikipedia.org/wiki/Line_code, but it is not obvious to me why 4b5b and 8b10b are called line code.
What is the fundamental difference between line code and more sophisticated hamming code?
What is the fundamental difference between line code and more sophisticated hamming code?
They're both serving entirely different purposes.
A line code enables clock recovery on a single, serial bit stream and provides bit-level synchronization. It may also provide byte-level synchronization. On differential electrical cabling, the line code (often in combination with a scrambler) also needs to remove DC bias.
A hamming code adds redundant bits for forward error correction.
The fundamental difference is the purpose of the code.
A line code is used to condition the data on a transmission line. Generally to balance the number of 0 and 1 bits sent to balance the current (what both 4b5b and 8b10b codes so)
A hamming code is used for error correction -- to detect transmission errors and possibly correct for them.
I need to check the value of a signal after a certain amount of time a clock edge occurs. For example, I want to check that if signal b asserts to high 1ps after posedge clock occurs.
Does SVA provide a syntax for this?
system-verilog-assertions were not intended for use as gate-level timing checks. Verilog already provides a number of built-in and optimized timing checks like $setuphold and $skew. See section 31. Timing checks in the IEEE 1800-2017 SystemVerilog LRM.
Timing checks are usually expressed as limits—either assertion happens at least 1ps after the clock edge, or at most 1ps after the clock edge. Also, must b be asserted after every clock edge? Regardless of the answers to these questions, it's possible to use SVA to model timing check, but you will have to manually create equations based on the actual requirements. For example
property p;
realtime timestamp;
#(posedge c) ($rose(a), timestamp = $realtime) |=>
#(posedge b) $realtime - timestamp < 1ps;
endproperty
I want to display an Error message when the signal reaches a certain value or simply when it reaches 0 I've used the ifblock and Relational Operatorbut it does not work for me.
You're most likely checking if the signal is exactly zero, which with floating point arithmetic is almost always a very bad thing to do.
Rather, you want to check that the absolute value of the signal is less than some small tolerance. More than that, you almost certainly need to check if the average of the signal over the past n-time points (where you choose n) is less than the tolerance.
You might also consider using something like the Static Gap block from the Model Verification library.
I see that assertions are always related to n number of cycles of a clock. Is there any way I can check the duration wrt timescale? Meaning
let's say I want to check if a reset is hold for 100ns or less, how do we write a assert statement for this?
Yes, conceptually you can write an assertion like this, using local variables in SVA.
It may look like this :
property reset_chk;
time current_time;
#(rst) (~rst, current_time = $time) |=> ($time - current_time == 100);
endproperty
But this type of assertions, should be avoided, as they are written not wrt clock.
Alternatively, one can always make a reference clock, fast enough to accommodate any such signal timings.
For local variables in assertion, you can read Local Variables in SVA
First I would consider whether SVA was the best way to check this at all.
If you think so, how about creating a dummy clock in the testbench with a suitable period and (via the power of hierarchical naming) use that. A suitable period might be
100ns if you were looking for a minimum pulse width
much faster if you were looking for a maximum pulse width (eg a 10ns period would allow you to check the pulse width was less than 110ns, ie 11 cycles).
Assertions are best done synchronously. That doesn't mean you cannot check asynchronous things, but you still need to sample the signals in question synchronously. So, this way you are sampling your asynchronous signal synchronously, using your dummy clock.
This is asynchronous check. The best way is to check it in traditional way or pure systemverilog instead of using SVA concurrent assertion.
If you want, you can still add immediate assertion for coverage purpose.
Quick sample code:
//
task assert_reset_hold_100ns();
fork : fk1
begin : blk1
#(reset);
$fatal;
end
begin : blk2
#100ns;
ASSERT_RESET_HOLD_100NS: assert(1);
end
join_any
disable fork;
endtask
// checker
initial forever begin
wait(reset === 0);
assert_reset_hold_100ns();
wait(reset === 1);
end
//
I am verifying part of a design which generates pulses with precisely timed edges. I have a basic behavioral model which produces an output which is similar, but not exactly the same as the design. The differences between the two are smaller than the precision needed for the design, so my model is good enough. The problem is: how do I do a comparison between these two signals?
I tried:
assert(out1 == out1_behav);
But that fails since the two signals have edges which happen 1ps apart. The design only requires that the edges be placed with 100ps precision, so I want a pass in this situation.
I thought about using a specify block with $delay() timing checks, however this causes me other problems since I need to run with +no_timing_checks to keep my ram models from failing in this RTL sim.
Is there a simple way to check that these edges are "almost" the same?
With the design requirement for the the signals to match within 100ps you could add a compare logic will a 100ps transition delay to act as a filter.
bit match;
assign #100ps match = (out1 == out1_behav);
always #*
assert #0 (match==1);
Verilog has different ways of assigning delay: transition and transport. Transition delays control the rise, fall, and indeterminate/high-Z timing. They can act as a filter if a driving signal gives a pulse less then the delay. Transport delays will always follow the the driving signals with a time shift. When the delays are large transition and transport will look the same.
assign #delay transition = driver; // Transition delay
always #(rhs) transport <= #dealy driver; // Transport delay
example: http://www.edaplayground.com/s/6/878, click the run button to see the waveform.
If you are using Modelsim/Questa, you can still use +notimingchecks, and then use the tcl command tchech_set to turn on individual timing checks, like $fullskew
Otherwise you will have to write a behavioral block that records the timestamps of the rising and falling edges of the two signals and checks the absolute value of the difference.